[test] Add missing REQUIRES: arm-registered-target

llvm · Jul 20, 2022 · 19d4f5e · 19d4f5e
1 parent adc1c34
commit 19d4f5e
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/llvm/test/Transforms/CodeGenPrepare/dead-allocation.ll b/llvm/test/Transforms/CodeGenPrepare/dead-allocation.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; Eliminate the dead allocation instruction
+; REQUIRES: arm-registered-target
 ; RUN: opt -codegenprepare < %s -S | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"