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[InstCombine] Optimize implementations of min/max for bool
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umin.i1 -> and : https://alive2.llvm.org/ce/z/6FNH6k
smin.i1 -> or : https://alive2.llvm.org/ce/z/h96S6o
umax.i1 -> or : https://alive2.llvm.org/ce/z/XHdeVk
smax.i1 -> and : https://alive2.llvm.org/ce/z/fkxKJx
umin.v4i1 -> and : https://alive2.llvm.org/ce/z/yV4VgP
smin.v4i1 -> or : https://alive2.llvm.org/ce/z/e9TF68
umax.v4i1 -> or : https://alive2.llvm.org/ce/z/tfNyfK
smax.v4i1 -> and : https://alive2.llvm.org/ce/z/0__Af2

Reviewed By: goldstein.w.n, bryanpkc

Differential Revision: https://reviews.llvm.org/D158915
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@Qi-Hu @bryanpkc
Qi-Hu authored and bryanpkc committed Sep 7, 2023
1 parent 149a698 commit 1a65cd3
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Showing 2 changed files with 22 additions and 8 deletions.
14 changes: 14 additions & 0 deletions llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1630,6 +1630,20 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
}
}

// umin(i1 X, i1 Y) -> and i1 X, Y
// smax(i1 X, i1 Y) -> and i1 X, Y
if ((IID == Intrinsic::umin || IID == Intrinsic::smax) &&
II->getType()->isIntOrIntVectorTy(1)) {
return BinaryOperator::CreateAnd(I0, I1);
}

// umax(i1 X, i1 Y) -> or i1 X, Y
// smin(i1 X, i1 Y) -> or i1 X, Y
if ((IID == Intrinsic::umax || IID == Intrinsic::smin) &&
II->getType()->isIntOrIntVectorTy(1)) {
return BinaryOperator::CreateOr(I0, I1);
}

if (IID == Intrinsic::smax || IID == Intrinsic::smin) {
// smax (neg nsw X), (neg nsw Y) --> neg nsw (smin X, Y)
// smin (neg nsw X), (neg nsw Y) --> neg nsw (smax X, Y)
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16 changes: 8 additions & 8 deletions llvm/test/Transforms/InstCombine/fold-minmax-i1.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
define i1 @umin_scalar(i1 %0, i1 %1) {
; CHECK-LABEL: define i1 @umin_scalar
; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.umin.i1(i1 [[TMP0]], i1 [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%3 = call i1 @llvm.umin.i1(i1 %0, i1 %1)
Expand All @@ -18,7 +18,7 @@ define i1 @umin_scalar(i1 %0, i1 %1) {
define i1 @smin_scalar(i1 %0, i1 %1) {
; CHECK-LABEL: define i1 @smin_scalar
; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.smin.i1(i1 [[TMP0]], i1 [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%3 = call i1 @llvm.smin.i1(i1 %0, i1 %1)
Expand All @@ -28,7 +28,7 @@ define i1 @smin_scalar(i1 %0, i1 %1) {
define i1 @umax_scalar(i1 %0, i1 %1) {
; CHECK-LABEL: define i1 @umax_scalar
; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.umax.i1(i1 [[TMP0]], i1 [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%3 = call i1 @llvm.umax.i1(i1 %0, i1 %1)
Expand All @@ -38,7 +38,7 @@ define i1 @umax_scalar(i1 %0, i1 %1) {
define i1 @smax_scalar(i1 %0, i1 %1) {
; CHECK-LABEL: define i1 @smax_scalar
; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.smax.i1(i1 [[TMP0]], i1 [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret i1 [[TMP3]]
;
%3 = call i1 @llvm.smax.i1(i1 %0, i1 %1)
Expand All @@ -52,7 +52,7 @@ define i1 @smax_scalar(i1 %0, i1 %1) {
define <4 x i1> @umin_vector(<4 x i1> %0, <4 x i1> %1) {
; CHECK-LABEL: define <4 x i1> @umin_vector
; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.umin.v4i1(<4 x i1> [[TMP0]], <4 x i1> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i1> [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret <4 x i1> [[TMP3]]
;
%3 = call <4 x i1> @llvm.umin.v4i1(<4 x i1> %0, <4 x i1> %1)
Expand All @@ -62,7 +62,7 @@ define <4 x i1> @umin_vector(<4 x i1> %0, <4 x i1> %1) {
define <4 x i1> @smin_vector(<4 x i1> %0, <4 x i1> %1) {
; CHECK-LABEL: define <4 x i1> @smin_vector
; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.smin.v4i1(<4 x i1> [[TMP0]], <4 x i1> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i1> [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret <4 x i1> [[TMP3]]
;
%3 = call <4 x i1> @llvm.smin.v4i1(<4 x i1> %0, <4 x i1> %1)
Expand All @@ -72,7 +72,7 @@ define <4 x i1> @smin_vector(<4 x i1> %0, <4 x i1> %1) {
define <4 x i1> @umax_vector(<4 x i1> %0, <4 x i1> %1) {
; CHECK-LABEL: define <4 x i1> @umax_vector
; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.umax.v4i1(<4 x i1> [[TMP0]], <4 x i1> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i1> [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret <4 x i1> [[TMP3]]
;
%3 = call <4 x i1> @llvm.umax.v4i1(<4 x i1> %0, <4 x i1> %1)
Expand All @@ -82,7 +82,7 @@ define <4 x i1> @umax_vector(<4 x i1> %0, <4 x i1> %1) {
define <4 x i1> @smax_vector(<4 x i1> %0, <4 x i1> %1) {
; CHECK-LABEL: define <4 x i1> @smax_vector
; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.smax.v4i1(<4 x i1> [[TMP0]], <4 x i1> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i1> [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret <4 x i1> [[TMP3]]
;
%3 = call <4 x i1> @llvm.smax.v4i1(<4 x i1> %0, <4 x i1> %1)
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