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[RISCV] Add IsSignExtendingOpW to AMO*_W instructions. (#72349)
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@topperc
topperc committed Nov 15, 2023
1 parent e12677d commit 1c033aa
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Showing 3 changed files with 48 additions and 45 deletions.
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoA.td
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Original file line number Diff line number Diff line change
Expand Up @@ -52,6 +52,8 @@ let Predicates = [HasStdExtA] in {
defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;

let IsSignExtendingOpW = 1 in {
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
Expand All @@ -70,6 +72,7 @@ defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
}
} // Predicates = [HasStdExtA]

let Predicates = [HasStdExtA, IsRV64] in {
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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -366,6 +366,8 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
// Copying from X0 produces zero.
case RISCV::COPY:
return MI.getOperand(1).getReg() == RISCV::X0;
case RISCV::PseudoAtomicLoadNand32:
return true;
}

return false;
Expand All @@ -384,6 +386,11 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
if (!SrcMI)
return false;
// Code assumes the register is operand 0.
// TODO: Maybe the worklist should store register?
if (!SrcMI->getOperand(0).isReg() ||
SrcMI->getOperand(0).getReg() != SrcReg)
return false;
// Add SrcMI to the worklist.
Worklist.push_back(SrcMI);
return true;
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83 changes: 38 additions & 45 deletions llvm/test/CodeGen/RISCV/atomic-signext.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4257,14 +4257,13 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: beqz a1, .LBB53_2
; RV64IA-NEXT: # %bb.1: # %then
; RV64IA-NEXT: li a1, 1
; RV64IA-NEXT: amoswap.w a1, a1, (a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: amoswap.w a0, a1, (a0)
; RV64IA-NEXT: ret
; RV64IA-NEXT: .LBB53_2: # %else
; RV64IA-NEXT: lw a1, 0(a0)
; RV64IA-NEXT: mv a1, a0
; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: li a2, 1
; RV64IA-NEXT: sw a2, 0(a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
br i1 %c, label %then, label %else

Expand Down Expand Up @@ -4345,14 +4344,13 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: beqz a1, .LBB54_2
; RV64IA-NEXT: # %bb.1: # %then
; RV64IA-NEXT: li a1, 1
; RV64IA-NEXT: amoadd.w a1, a1, (a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret
; RV64IA-NEXT: .LBB54_2: # %else
; RV64IA-NEXT: lw a1, 0(a0)
; RV64IA-NEXT: addi a2, a1, 1
; RV64IA-NEXT: sw a2, 0(a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: mv a1, a0
; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: addi a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
br i1 %c, label %then, label %else

Expand Down Expand Up @@ -4434,14 +4432,13 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: beqz a1, .LBB55_2
; RV64IA-NEXT: # %bb.1: # %then
; RV64IA-NEXT: li a1, -1
; RV64IA-NEXT: amoadd.w a1, a1, (a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: amoadd.w a0, a1, (a0)
; RV64IA-NEXT: ret
; RV64IA-NEXT: .LBB55_2: # %else
; RV64IA-NEXT: lw a1, 0(a0)
; RV64IA-NEXT: addi a2, a1, -1
; RV64IA-NEXT: sw a2, 0(a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: mv a1, a0
; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: addi a2, a0, -1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
br i1 %c, label %then, label %else

Expand Down Expand Up @@ -4523,14 +4520,13 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: beqz a1, .LBB56_2
; RV64IA-NEXT: # %bb.1: # %then
; RV64IA-NEXT: li a1, 1
; RV64IA-NEXT: amoand.w a1, a1, (a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: amoand.w a0, a1, (a0)
; RV64IA-NEXT: ret
; RV64IA-NEXT: .LBB56_2: # %else
; RV64IA-NEXT: lwu a1, 0(a0)
; RV64IA-NEXT: andi a2, a1, 1
; RV64IA-NEXT: sw a2, 0(a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: mv a1, a0
; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: andi a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
br i1 %c, label %then, label %else

Expand Down Expand Up @@ -4615,25 +4611,24 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
;
; RV64IA-LABEL: atomicrmw_nand_i32_monotonic_crossbb:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a1, a1, 1
; RV64IA-NEXT: beqz a1, .LBB57_2
; RV64IA-NEXT: andi a2, a1, 1
; RV64IA-NEXT: mv a1, a0
; RV64IA-NEXT: beqz a2, .LBB57_2
; RV64IA-NEXT: # %bb.1: # %then
; RV64IA-NEXT: li a2, 1
; RV64IA-NEXT: .LBB57_3: # %then
; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a1, (a0)
; RV64IA-NEXT: and a3, a1, a2
; RV64IA-NEXT: lr.w a0, (a1)
; RV64IA-NEXT: and a3, a0, a2
; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w a3, a3, (a0)
; RV64IA-NEXT: sc.w a3, a3, (a1)
; RV64IA-NEXT: bnez a3, .LBB57_3
; RV64IA-NEXT: # %bb.4: # %then
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: ret
; RV64IA-NEXT: .LBB57_2: # %else
; RV64IA-NEXT: lwu a1, 0(a0)
; RV64IA-NEXT: andi a2, a1, 1
; RV64IA-NEXT: sw a2, 0(a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: lw a0, 0(a1)
; RV64IA-NEXT: andi a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
br i1 %c, label %then, label %else

Expand Down Expand Up @@ -4715,14 +4710,13 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind {
; RV64IA-NEXT: beqz a1, .LBB58_2
; RV64IA-NEXT: # %bb.1: # %then
; RV64IA-NEXT: li a1, 1
; RV64IA-NEXT: amoor.w a1, a1, (a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: amoor.w a0, a1, (a0)
; RV64IA-NEXT: ret
; RV64IA-NEXT: .LBB58_2: # %else
; RV64IA-NEXT: lw a1, 0(a0)
; RV64IA-NEXT: ori a2, a1, 1
; RV64IA-NEXT: sw a2, 0(a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: mv a1, a0
; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: ori a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
br i1 %c, label %then, label %else

Expand Down Expand Up @@ -4804,14 +4798,13 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64IA-NEXT: beqz a1, .LBB59_2
; RV64IA-NEXT: # %bb.1: # %then
; RV64IA-NEXT: li a1, 1
; RV64IA-NEXT: amoxor.w a1, a1, (a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: amoxor.w a0, a1, (a0)
; RV64IA-NEXT: ret
; RV64IA-NEXT: .LBB59_2: # %else
; RV64IA-NEXT: lw a1, 0(a0)
; RV64IA-NEXT: xori a2, a1, 1
; RV64IA-NEXT: sw a2, 0(a0)
; RV64IA-NEXT: sext.w a0, a1
; RV64IA-NEXT: mv a1, a0
; RV64IA-NEXT: lw a0, 0(a0)
; RV64IA-NEXT: xori a2, a0, 1
; RV64IA-NEXT: sw a2, 0(a1)
; RV64IA-NEXT: ret
br i1 %c, label %then, label %else

Expand Down

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