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[VE] Disable automatic maxnum/minnum selection
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Disable FMAX/FMIN selection from select_cc in VEInstrInfo.td because of
the lack of NaN consideration.  This patch removes such selection from
VEInstrInfo.td and lets llvm work on it in combineMinNumMaxNum.

Reviewed By: efocht

Differential Revision: https://reviews.llvm.org/D134595
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@kaz7
kaz7 committed Sep 26, 2022
1 parent ab3779a commit 1cef30b
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Showing 3 changed files with 217 additions and 31 deletions.
23 changes: 0 additions & 23 deletions llvm/lib/Target/VE/VEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2052,29 +2052,6 @@ def : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)),
def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)),
(setccrr<CMOVDrm> (fcond2cc $cond), (FCMPQrr $l, $r))>;

// Special SELECTCC pattern matches
// Use min/max for better performance.
//
// MAX/MIN %res, %lhs, %rhs

def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGT)),
(FMAXDrr $LHS, $RHS)>;
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGT)),
(FMAXSrr $LHS, $RHS)>;
def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGE)),
(FMAXDrr $LHS, $RHS)>;
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGE)),
(FMAXSrr $LHS, $RHS)>;

def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLT)),
(FMINDrr $LHS, $RHS)>;
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLT)),
(FMINSrr $LHS, $RHS)>;
def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLE)),
(FMINDrr $LHS, $RHS)>;
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLE)),
(FMINSrr $LHS, $RHS)>;

// Helper classes to construct cmov patterns for the ease.
//
// Hiding INSERT_SUBREG/EXTRACT_SUBREG patterns.
Expand Down
111 changes: 107 additions & 4 deletions llvm/test/CodeGen/VE/Scalar/max.ll
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Original file line number Diff line number Diff line change
@@ -1,11 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
; RUN: llc < %s -mtriple=ve-unknown-unknown -enable-no-signed-zeros-fp-math \
; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=OPT

define double @maxf64(double, double) {
; CHECK-LABEL: maxf64:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.d %s0, %s0, %s1
; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxf64:
; OPT: # %bb.0:
; OPT-NEXT: fmax.d %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
Expand All @@ -14,8 +23,15 @@ define double @maxf64(double, double) {
define double @max2f64(double, double) {
; CHECK-LABEL: max2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.d %s0, %s0, %s1
; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2f64:
; OPT: # %bb.0:
; OPT-NEXT: fmax.d %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
Expand All @@ -29,6 +45,11 @@ define double @maxuf64(double, double) {
; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxuf64:
; OPT: # %bb.0:
; OPT-NEXT: fmax.d %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
Expand All @@ -42,6 +63,11 @@ define double @max2uf64(double, double) {
; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2uf64:
; OPT: # %bb.0:
; OPT-NEXT: fmax.d %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
Expand All @@ -50,8 +76,15 @@ define double @max2uf64(double, double) {
define float @maxf32(float, float) {
; CHECK-LABEL: maxf32:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.s %s0, %s0, %s1
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxf32:
; OPT: # %bb.0:
; OPT-NEXT: fmax.s %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
Expand All @@ -60,8 +93,15 @@ define float @maxf32(float, float) {
define float @max2f32(float, float) {
; CHECK-LABEL: max2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.s %s0, %s0, %s1
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2f32:
; OPT: # %bb.0:
; OPT-NEXT: fmax.s %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
Expand All @@ -74,6 +114,11 @@ define float @maxuf32(float, float) {
; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxuf32:
; OPT: # %bb.0:
; OPT-NEXT: fmax.s %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
Expand All @@ -86,6 +131,11 @@ define float @max2uf32(float, float) {
; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2uf32:
; OPT: # %bb.0:
; OPT-NEXT: fmax.s %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
Expand All @@ -96,6 +146,11 @@ define i64 @maxi64(i64, i64) {
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxi64:
; OPT: # %bb.0:
; OPT-NEXT: maxs.l %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
Expand All @@ -106,6 +161,11 @@ define i64 @max2i64(i64, i64) {
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2i64:
; OPT: # %bb.0:
; OPT-NEXT: maxs.l %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
Expand All @@ -118,6 +178,13 @@ define i64 @maxu64(i64, i64) {
; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxu64:
; OPT: # %bb.0:
; OPT-NEXT: cmpu.l %s2, %s0, %s1
; OPT-NEXT: cmov.l.gt %s1, %s0, %s2
; OPT-NEXT: or %s0, 0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
Expand All @@ -130,6 +197,13 @@ define i64 @max2u64(i64, i64) {
; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2u64:
; OPT: # %bb.0:
; OPT-NEXT: cmpu.l %s2, %s0, %s1
; OPT-NEXT: cmov.l.ge %s1, %s0, %s2
; OPT-NEXT: or %s0, 0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
Expand All @@ -140,6 +214,11 @@ define i32 @maxi32(i32, i32) {
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxi32:
; OPT: # %bb.0:
; OPT-NEXT: maxs.w.sx %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
Expand All @@ -150,6 +229,11 @@ define i32 @max2i32(i32, i32) {
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2i32:
; OPT: # %bb.0:
; OPT-NEXT: maxs.w.sx %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
Expand All @@ -162,6 +246,13 @@ define i32 @maxu32(i32, i32) {
; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxu32:
; OPT: # %bb.0:
; OPT-NEXT: cmpu.w %s2, %s0, %s1
; OPT-NEXT: cmov.w.gt %s1, %s0, %s2
; OPT-NEXT: or %s0, 0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
Expand All @@ -174,6 +265,13 @@ define i32 @max2u32(i32, i32) {
; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: max2u32:
; OPT: # %bb.0:
; OPT-NEXT: cmpu.w %s2, %s0, %s1
; OPT-NEXT: cmov.w.ge %s1, %s0, %s2
; OPT-NEXT: or %s0, 0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
Expand All @@ -184,6 +282,11 @@ define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) {
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: b.l.t (, %s10)
;
; OPT-LABEL: maxi1:
; OPT: # %bb.0:
; OPT-NEXT: or %s0, %s0, %s1
; OPT-NEXT: b.l.t (, %s10)
%3 = xor i1 %1, true
%4 = and i1 %3, %0
%5 = select i1 %4, i1 %0, i1 %1
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