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[GlobalISel][X86] Get correct RegClass for given RegBank.
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Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665

Reviewers: qcolombet, t.p.northover, zvi, guyblank

Reviewed By: t.p.northover, guyblank

Subscribers: guyblank, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33952

Conflicts:
	test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

llvm-svn: 305784
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Igor Breger committed Jun 20, 2017
1 parent 14535f0 commit 1dcd5e8
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Showing 2 changed files with 44 additions and 23 deletions.
43 changes: 26 additions & 17 deletions llvm/lib/Target/X86/X86InstructionSelector.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,9 +72,13 @@ class X86InstructionSelector : public InstructionSelector {
MachineFunction &MF) const;
bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;

bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;

const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
MachineRegisterInfo &MRI) const;

const X86TargetMachine &TM;
const X86Subtarget &STI;
Expand Down Expand Up @@ -113,8 +117,8 @@ X86InstructionSelector::X86InstructionSelector(const X86TargetMachine &TM,

// FIXME: This should be target-independent, inferred from the types declared
// for each class in the bank.
static const TargetRegisterClass *
getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) {
const TargetRegisterClass *
X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
if (RB.getID() == X86::GPRRegBankID) {
if (Ty.getSizeInBits() <= 8)
return &X86::GR8RegClass;
Expand All @@ -127,24 +131,30 @@ getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) {
}
if (RB.getID() == X86::VECRRegBankID) {
if (Ty.getSizeInBits() == 32)
return &X86::FR32XRegClass;
return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
if (Ty.getSizeInBits() == 64)
return &X86::FR64XRegClass;
return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
if (Ty.getSizeInBits() == 128)
return &X86::VR128XRegClass;
return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass;
if (Ty.getSizeInBits() == 256)
return &X86::VR256XRegClass;
return STI.hasAVX512() ? &X86::VR256XRegClass : &X86::VR256RegClass;
if (Ty.getSizeInBits() == 512)
return &X86::VR512RegClass;
}

llvm_unreachable("Unknown RegBank!");
}

const TargetRegisterClass *
X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
MachineRegisterInfo &MRI) const {
const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
return getRegClass(Ty, RegBank);
}

// Set X86 Opcode and constrain DestReg.
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) {
bool X86InstructionSelector::selectCopy(MachineInstr &I,
MachineRegisterInfo &MRI) const {

unsigned DstReg = I.getOperand(0).getReg();
if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
Expand All @@ -171,7 +181,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
switch (RegBank.getID()) {
case X86::GPRRegBankID:
assert((DstSize <= 64) && "GPRs cannot get more than 64-bit width values.");
RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
RC = getRegClass(MRI.getType(DstReg), RegBank);

// Change the physical register
if (SrcSize > DstSize && TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
Expand All @@ -186,7 +196,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
}
break;
case X86::VECRRegBankID:
RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
RC = getRegClass(MRI.getType(DstReg), RegBank);
break;
default:
llvm_unreachable("Unknown RegBank!");
Expand Down Expand Up @@ -220,7 +230,7 @@ bool X86InstructionSelector::select(MachineInstr &I) const {
// Certain non-generic instructions also need some special handling.

if (I.isCopy())
return selectCopy(I, TII, MRI, TRI, RBI);
return selectCopy(I, MRI);

// TODO: handle more cases - LOAD_STACK_GUARD, PHI
return true;
Expand Down Expand Up @@ -499,11 +509,11 @@ bool X86InstructionSelector::selectTrunc(MachineInstr &I,
if (DstRB.getID() != X86::GPRRegBankID)
return false;

const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
if (!DstRC)
return false;

const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB);
const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
if (!SrcRC)
return false;

Expand Down Expand Up @@ -558,8 +568,7 @@ bool X86InstructionSelector::selectZext(MachineInstr &I,
return false;

const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
unsigned DefReg =
MRI.createVirtualRegister(getRegClassForTypeOnBank(DstTy, RegBank));
unsigned DefReg = MRI.createVirtualRegister(getRegClass(DstTy, RegBank));

BuildMI(*I.getParent(), I, I.getDebugLoc(),
TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
Expand Down
24 changes: 18 additions & 6 deletions llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -354,10 +354,16 @@ name: test_store_float
alignment: 4
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 2, class: gr32, preferred-register: '' }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
# ALL: - { id: 0, class: fr32x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
# ALL: - { id: 2, class: gr32, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
Expand Down Expand Up @@ -413,10 +419,16 @@ name: test_store_double
alignment: 4
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 2, class: gr64, preferred-register: '' }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
registers:
# ALL: - { id: 0, class: fr64x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
# ALL: - { id: 2, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
Expand Down

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