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[RISCV][llvm-mca] Add mca tests for riscv lmul instruments
Add llvm-mca tests for RISCV LMUL instruments to show that llvm-mca RISCV LMUL instruments work. This commit was previously reverted in ad8765a. This commit adds a lit.local.cfg to make RISCV llvm-mca tests unsupported on non-RISCV configurations. Differential Revision: https://reviews.llvm.org/D149496
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,76 @@ | ||
| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
| # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s | ||
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||
| vsetvli zero, a0, e8, m1, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL M1 | ||
| vadd.vv v12, v12, v12 | ||
| vsetvli zero, a0, e8, m8, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL M8 | ||
| vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Iterations: 1 | ||
| # CHECK-NEXT: Instructions: 4 | ||
| # CHECK-NEXT: Total Cycles: 12 | ||
| # CHECK-NEXT: Total uOps: 4 | ||
|
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||
| # CHECK: Dispatch Width: 2 | ||
| # CHECK-NEXT: uOps Per Cycle: 0.33 | ||
| # CHECK-NEXT: IPC: 0.33 | ||
| # CHECK-NEXT: Block RThroughput: 18.0 | ||
|
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||
| # CHECK: Instruction Info: | ||
| # CHECK-NEXT: [1]: #uOps | ||
| # CHECK-NEXT: [2]: Latency | ||
| # CHECK-NEXT: [3]: RThroughput | ||
| # CHECK-NEXT: [4]: MayLoad | ||
| # CHECK-NEXT: [5]: MayStore | ||
| # CHECK-NEXT: [6]: HasSideEffects (U) | ||
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||
| # CHECK: [1] [2] [3] [4] [5] [6] Instructions: | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Resources: | ||
| # CHECK-NEXT: [0] - SiFive7FDiv | ||
| # CHECK-NEXT: [1] - SiFive7IDiv | ||
| # CHECK-NEXT: [2] - SiFive7PipeA | ||
| # CHECK-NEXT: [3] - SiFive7PipeB | ||
| # CHECK-NEXT: [4] - SiFive7PipeV | ||
| # CHECK-NEXT: [5] - SiFive7VA | ||
| # CHECK-NEXT: [6] - SiFive7VL | ||
| # CHECK-NEXT: [7] - SiFive7VS | ||
|
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||
| # CHECK: Resource pressure per iteration: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] | ||
| # CHECK-NEXT: - - 2.00 - 18.00 18.00 - - | ||
|
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||
| # CHECK: Resource pressure by instruction: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 | ||
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||
| # CHECK: Timeline view: | ||
| # CHECK-NEXT: 01 | ||
| # CHECK-NEXT: Index 0123456789 | ||
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||
| # CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12 | ||
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||
| # CHECK: Average Wait times (based on the timeline view): | ||
| # CHECK-NEXT: [0]: Executions | ||
| # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue | ||
| # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready | ||
| # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage | ||
|
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||
| # CHECK: [0] [1] [2] [3] | ||
| # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 0.0 0.0 0.0 <total> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,87 @@ | ||
| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
| # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 -disable-im < %s | FileCheck %s | ||
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||
| vsetvli zero, a0, e8, m2, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL M2 | ||
| vadd.vv v12, v12, v12 | ||
| vsetvli zero, a0, e8, m1, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL M1 | ||
| vadd.vv v12, v12, v12 | ||
| vsetvli zero, a0, e8, m8, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL M8 | ||
| vadd.vv v12, v12, v12 | ||
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||
| # CHECK: Iterations: 1 | ||
| # CHECK-NEXT: Instructions: 6 | ||
| # CHECK-NEXT: Total Cycles: 40 | ||
| # CHECK-NEXT: Total uOps: 6 | ||
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||
| # CHECK: Dispatch Width: 2 | ||
| # CHECK-NEXT: uOps Per Cycle: 0.15 | ||
| # CHECK-NEXT: IPC: 0.15 | ||
| # CHECK-NEXT: Block RThroughput: 48.0 | ||
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||
| # CHECK: Instruction Info: | ||
| # CHECK-NEXT: [1]: #uOps | ||
| # CHECK-NEXT: [2]: Latency | ||
| # CHECK-NEXT: [3]: RThroughput | ||
| # CHECK-NEXT: [4]: MayLoad | ||
| # CHECK-NEXT: [5]: MayStore | ||
| # CHECK-NEXT: [6]: HasSideEffects (U) | ||
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||
| # CHECK: [1] [2] [3] [4] [5] [6] Instructions: | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
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||
| # CHECK: Resources: | ||
| # CHECK-NEXT: [0] - SiFive7FDiv | ||
| # CHECK-NEXT: [1] - SiFive7IDiv | ||
| # CHECK-NEXT: [2] - SiFive7PipeA | ||
| # CHECK-NEXT: [3] - SiFive7PipeB | ||
| # CHECK-NEXT: [4] - SiFive7PipeV | ||
| # CHECK-NEXT: [5] - SiFive7VA | ||
| # CHECK-NEXT: [6] - SiFive7VL | ||
| # CHECK-NEXT: [7] - SiFive7VS | ||
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||
| # CHECK: Resource pressure per iteration: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] | ||
| # CHECK-NEXT: - - 3.00 - 48.00 48.00 - - | ||
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||
| # CHECK: Resource pressure by instruction: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu | ||
| # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 | ||
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||
| # CHECK: Timeline view: | ||
| # CHECK-NEXT: 0123456789 0123456789 | ||
| # CHECK-NEXT: Index 0123456789 0123456789 | ||
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||
| # CHECK: [0,0] DeeE . . . . . . . . vsetvli zero, a0, e8, m2, tu, mu | ||
| # CHECK-NEXT: [0,1] . DeeeE . . . . . . . vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: [0,2] . DeeE . . . . . . . vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: [0,3] . . . . DeeeE . . . . vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: [0,4] . . . . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: [0,5] . . . . . . . DeeeE vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Average Wait times (based on the timeline view): | ||
| # CHECK-NEXT: [0]: Executions | ||
| # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue | ||
| # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready | ||
| # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage | ||
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||
| # CHECK: [0] [1] [2] [3] | ||
| # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu | ||
| # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: 5. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 0.0 0.0 0.0 <total> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,64 @@ | ||
| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
| # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s | ||
|
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||
| vsetvli zero, a0, e8, m1, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL M1 | ||
| vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Iterations: 1 | ||
| # CHECK-NEXT: Instructions: 2 | ||
| # CHECK-NEXT: Total Cycles: 8 | ||
| # CHECK-NEXT: Total uOps: 2 | ||
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||
| # CHECK: Dispatch Width: 2 | ||
| # CHECK-NEXT: uOps Per Cycle: 0.25 | ||
| # CHECK-NEXT: IPC: 0.25 | ||
| # CHECK-NEXT: Block RThroughput: 2.0 | ||
|
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||
| # CHECK: Instruction Info: | ||
| # CHECK-NEXT: [1]: #uOps | ||
| # CHECK-NEXT: [2]: Latency | ||
| # CHECK-NEXT: [3]: RThroughput | ||
| # CHECK-NEXT: [4]: MayLoad | ||
| # CHECK-NEXT: [5]: MayStore | ||
| # CHECK-NEXT: [6]: HasSideEffects (U) | ||
|
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||
| # CHECK: [1] [2] [3] [4] [5] [6] Instructions: | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Resources: | ||
| # CHECK-NEXT: [0] - SiFive7FDiv | ||
| # CHECK-NEXT: [1] - SiFive7IDiv | ||
| # CHECK-NEXT: [2] - SiFive7PipeA | ||
| # CHECK-NEXT: [3] - SiFive7PipeB | ||
| # CHECK-NEXT: [4] - SiFive7PipeV | ||
| # CHECK-NEXT: [5] - SiFive7VA | ||
| # CHECK-NEXT: [6] - SiFive7VL | ||
| # CHECK-NEXT: [7] - SiFive7VS | ||
|
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||
| # CHECK: Resource pressure per iteration: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] | ||
| # CHECK-NEXT: - - 1.00 - 2.00 2.00 - - | ||
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| # CHECK: Resource pressure by instruction: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 | ||
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||
| # CHECK: Timeline view: | ||
| # CHECK-NEXT: Index 01234567 | ||
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||
| # CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 | ||
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||
| # CHECK: Average Wait times (based on the timeline view): | ||
| # CHECK-NEXT: [0]: Executions | ||
| # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue | ||
| # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready | ||
| # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage | ||
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| # CHECK: [0] [1] [2] [3] | ||
| # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 0.0 0.0 0.0 <total> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,70 @@ | ||
| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
| # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s | ||
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||
| vadd.vv v12, v12, v12 | ||
| vsetvli zero, a0, e8, m8, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL MF8 | ||
| vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Iterations: 1 | ||
| # CHECK-NEXT: Instructions: 3 | ||
| # CHECK-NEXT: Total Cycles: 21 | ||
| # CHECK-NEXT: Total uOps: 3 | ||
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||
| # CHECK: Dispatch Width: 2 | ||
| # CHECK-NEXT: uOps Per Cycle: 0.14 | ||
| # CHECK-NEXT: IPC: 0.14 | ||
| # CHECK-NEXT: Block RThroughput: 17.0 | ||
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||
| # CHECK: Instruction Info: | ||
| # CHECK-NEXT: [1]: #uOps | ||
| # CHECK-NEXT: [2]: Latency | ||
| # CHECK-NEXT: [3]: RThroughput | ||
| # CHECK-NEXT: [4]: MayLoad | ||
| # CHECK-NEXT: [5]: MayStore | ||
| # CHECK-NEXT: [6]: HasSideEffects (U) | ||
|
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||
| # CHECK: [1] [2] [3] [4] [5] [6] Instructions: | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Resources: | ||
| # CHECK-NEXT: [0] - SiFive7FDiv | ||
| # CHECK-NEXT: [1] - SiFive7IDiv | ||
| # CHECK-NEXT: [2] - SiFive7PipeA | ||
| # CHECK-NEXT: [3] - SiFive7PipeB | ||
| # CHECK-NEXT: [4] - SiFive7PipeV | ||
| # CHECK-NEXT: [5] - SiFive7VA | ||
| # CHECK-NEXT: [6] - SiFive7VL | ||
| # CHECK-NEXT: [7] - SiFive7VS | ||
|
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||
| # CHECK: Resource pressure per iteration: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] | ||
| # CHECK-NEXT: - - 1.00 - 17.00 17.00 - - | ||
|
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||
| # CHECK: Resource pressure by instruction: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: | ||
| # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Timeline view: | ||
| # CHECK-NEXT: 0123456789 | ||
| # CHECK-NEXT: Index 0123456789 0 | ||
|
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||
| # CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Average Wait times (based on the timeline view): | ||
| # CHECK-NEXT: [0]: Executions | ||
| # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue | ||
| # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready | ||
| # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage | ||
|
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||
| # CHECK: [0] [1] [2] [3] | ||
| # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu | ||
| # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 0.0 0.0 0.0 <total> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,68 @@ | ||
| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py | ||
| # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s | ||
|
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||
| # LLVM-MCA-BEGIN foo | ||
| vsetvli zero, a0, e8, m1, tu, mu | ||
| # LLVM-MCA-RISCV-LMUL M1 | ||
| vadd.vv v12, v12, v12 | ||
| # LLVM-MCA-END foo | ||
|
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||
| # CHECK: [0] Code Region - foo | ||
|
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||
| # CHECK: Iterations: 1 | ||
| # CHECK-NEXT: Instructions: 2 | ||
| # CHECK-NEXT: Total Cycles: 8 | ||
| # CHECK-NEXT: Total uOps: 2 | ||
|
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||
| # CHECK: Dispatch Width: 2 | ||
| # CHECK-NEXT: uOps Per Cycle: 0.25 | ||
| # CHECK-NEXT: IPC: 0.25 | ||
| # CHECK-NEXT: Block RThroughput: 2.0 | ||
|
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||
| # CHECK: Instruction Info: | ||
| # CHECK-NEXT: [1]: #uOps | ||
| # CHECK-NEXT: [2]: Latency | ||
| # CHECK-NEXT: [3]: RThroughput | ||
| # CHECK-NEXT: [4]: MayLoad | ||
| # CHECK-NEXT: [5]: MayStore | ||
| # CHECK-NEXT: [6]: HasSideEffects (U) | ||
|
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||
| # CHECK: [1] [2] [3] [4] [5] [6] Instructions: | ||
| # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 | ||
|
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||
| # CHECK: Resources: | ||
| # CHECK-NEXT: [0] - SiFive7FDiv | ||
| # CHECK-NEXT: [1] - SiFive7IDiv | ||
| # CHECK-NEXT: [2] - SiFive7PipeA | ||
| # CHECK-NEXT: [3] - SiFive7PipeB | ||
| # CHECK-NEXT: [4] - SiFive7PipeV | ||
| # CHECK-NEXT: [5] - SiFive7VA | ||
| # CHECK-NEXT: [6] - SiFive7VL | ||
| # CHECK-NEXT: [7] - SiFive7VS | ||
|
|
||
| # CHECK: Resource pressure per iteration: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] | ||
| # CHECK-NEXT: - - 1.00 - 2.00 2.00 - - | ||
|
|
||
| # CHECK: Resource pressure by instruction: | ||
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: | ||
| # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 | ||
|
|
||
| # CHECK: Timeline view: | ||
| # CHECK-NEXT: Index 01234567 | ||
|
|
||
| # CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 | ||
|
|
||
| # CHECK: Average Wait times (based on the timeline view): | ||
| # CHECK-NEXT: [0]: Executions | ||
| # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue | ||
| # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready | ||
| # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage | ||
|
|
||
| # CHECK: [0] [1] [2] [3] | ||
| # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu | ||
| # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 | ||
| # CHECK-NEXT: 1 0.0 0.0 0.0 <total> |
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