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[mips] Marked the Trap-on-Condition instructions as Mips II
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Patch by Vasileios Kalintiris.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5173

llvm-svn: 217255
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@dsandersllvm
dsandersllvm committed Sep 5, 2014
1 parent 3c24b04 commit 1fcea42
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Showing 12 changed files with 152 additions and 14 deletions.
34 changes: 20 additions & 14 deletions llvm/lib/Target/Mips/MipsInstrInfo.td
View file
Expand Up @@ -1148,12 +1148,13 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
}

def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;

def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;

def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
ISA_MIPS2_NOT_32R6_64R6;
Expand Down Expand Up @@ -1483,14 +1484,19 @@ def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
def : MipsInstAlias<"ei", (EI ZERO), 1>;
def : MipsInstAlias<"di", (DI ZERO), 1>;

def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1>;
def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1>;
def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tge $rs, $rt",
(TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tgeu $rs, $rt",
(TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tlt $rs, $rt",
(TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tltu $rs, $rt",
(TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tne $rs, $rt",
(TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;

def : MipsInstAlias<"sll $rd, $rt, $rs",
(SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sub, $rd, $rs, $imm",
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips1/invalid-mips2.s
View file
Expand Up @@ -13,11 +13,23 @@
round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
teq $0,$3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
teq $5,$7,620 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tge $7,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tge $5,$19,340 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tgeu $22,$28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tgeu $20,$14,379 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tlt $15,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tlt $2,$19,133 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tlti $t6,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tltu $11,$16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tltu $16,$29,1016 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tne $6,$17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tne $7,$8,885 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips2/valid.s
View file
Expand Up @@ -123,15 +123,27 @@
swl $15,13694($s3)
swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025
tgeiu $sp,-28621
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips3/valid.s
View file
Expand Up @@ -180,15 +180,27 @@
swl $15,13694($s3)
swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025
tgeiu $sp,-28621
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips32/valid.s
View file
Expand Up @@ -151,15 +151,27 @@
swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025
tgeiu $sp,-28621
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips32r2/valid.s
View file
Expand Up @@ -181,15 +181,27 @@
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025
tgeiu $sp,-28621
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips32r6/valid.s
View file
Expand Up @@ -152,3 +152,15 @@
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips4/valid.s
View file
Expand Up @@ -199,15 +199,27 @@
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025
tgeiu $sp,-28621
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/Mips/mips5/valid.s
View file
Expand Up @@ -201,15 +201,27 @@
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $s5,-17504
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $s1,5025
tgeiu $sp,-28621
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
Expand Down

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