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[AMDGPU] Extend WorkGroupID* codegen for compute shaders
Currently, the codegen support for llvm.amdgcn.workgroup.id* intrinsics are enabled only for compute kernels. In addition, this patch enables their selection for compute shaders on subtargets that have architected SGPRs. Differential Revision: https://reviews.llvm.org/D145045
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llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs --verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-SDAG %s | ||
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel --verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-GISEL %s | ||
define amdgpu_cs void @_amdgpu_cs_main() { | ||
; GFX9-SDAG-LABEL: _amdgpu_cs_main: | ||
; GFX9-SDAG: ; %bb.0: ; %.entry | ||
; GFX9-SDAG-NEXT: s_lshr_b32 s2, ttmp7, 16 | ||
; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff | ||
; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9 | ||
; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 | ||
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s2 | ||
; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 | ||
; GFX9-SDAG-NEXT: s_endpgm | ||
; | ||
; GFX9-GISEL-LABEL: _amdgpu_cs_main: | ||
; GFX9-GISEL: ; %bb.0: ; %.entry | ||
; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp9 | ||
; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff | ||
; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 | ||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 | ||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 | ||
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2 | ||
; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 | ||
; GFX9-GISEL-NEXT: s_endpgm | ||
.entry: | ||
%idx = call i32 @llvm.amdgcn.workgroup.id.x() | ||
%idy = call i32 @llvm.amdgcn.workgroup.id.y() | ||
%idz = call i32 @llvm.amdgcn.workgroup.id.z() | ||
%ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0 | ||
%ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1 | ||
%ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2 | ||
call void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32> %ielemz, <4 x i32> undef, i32 0, i32 0, i32 0) | ||
ret void | ||
} | ||
|
||
declare i32 @llvm.amdgcn.workgroup.id.x() | ||
declare i32 @llvm.amdgcn.workgroup.id.y() | ||
declare i32 @llvm.amdgcn.workgroup.id.z() | ||
declare void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32 immarg) |