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[ARM] Enable useAA() for the in-order Cortex-R52
This option allows codegen (such as DAGCombine or MI scheduling) to use alias analysis information, which can help with the codegen on in-order cpu's, especially machine scheduling. Here I have done things the same way as AArch64, adding a subtarget feature to enable this for specific cores, and enabled it for the R52 where we have a schedule to make use of it. Differential Revision: https://reviews.llvm.org/D48074 llvm-svn: 335249
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA | ||
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC | ||
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; Check we use AA during codegen, so can interleave these loads/stores. | ||
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; CHECK-LABEL: test | ||
; GENERIC: ldr | ||
; GENERIC: str | ||
; GENERIC: ldr | ||
; GENERIC: str | ||
; USEAA: ldr | ||
; USEAA: ldr | ||
; USEAA: str | ||
; USEAA: str | ||
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define void @test(i32* nocapture %a, i32* noalias nocapture %b) { | ||
entry: | ||
%0 = load i32, i32* %a, align 4 | ||
%add = add nsw i32 %0, 10 | ||
store i32 %add, i32* %a, align 4 | ||
%1 = load i32, i32* %b, align 4 | ||
%add2 = add nsw i32 %1, 20 | ||
store i32 %add2, i32* %b, align 4 | ||
ret void | ||
} | ||
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