LivePhysRegs: Automatically determine presence of pristine regs.

Remove the AddPristinesAndCSRs parameters from
addLiveIns()/addLiveOuts().

We need to respect pristine registers after prologue epilogue insertion,
Seeing that we got this wrong in at least two commits already, we should
rather pay the small price to query MachineFrameInfo for it.

There are three cases that did not set AddPristineAndCSRs to true even
after register allocation:
- ExecutionDepsFix: live-out registers are used as a hint that the
  register is used soon. This is not true for pristine registers so
  use the new addLiveOutsNoPristines() to maintain this behaviour.
- SystemZShortenInst: Not setting AddPristineAndCSRs to true looks like
  a bug, should do the right thing automatically now.
- StackMapLivenessAnalysis: Not adding pristine registers looks like a
  bug to me. Added a FIXME comment but maintain the current behaviour
  as a change may need to get coordinated with GC runtimes.

llvm-svn: 268336

llvm/include/llvm/CodeGen/LivePhysRegs.h

@@ -112,15 +112,20 @@ class LivePhysRegs {
   void stepForward(const MachineInstr &MI,
         SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> &Clobbers);
 
-  /// \brief Adds all live-in registers of basic block @p MBB; After prologue/
-  /// epilogue insertion \p AddPristines should be set to true to insert the
+  /// Adds all live-in registers of basic block @p MBB.
+  /// Live in registers are the registers in the blocks live-in list and the
   /// pristine registers.
-  void addLiveIns(const MachineBasicBlock *MBB, bool AddPristines = false);
+  void addLiveIns(const MachineBasicBlock *MBB);
 
-  /// \brief Adds all live-out registers of basic block @p MBB; After prologue/
-  /// epilogue insertion \p AddPristinesAndCSRs should be set to true.
-  void addLiveOuts(const MachineBasicBlock *MBB,
-                   bool AddPristinesAndCSRs = false);
+  /// Adds all live-out registers of basic block @p MBB.
+  /// Live out registers are the union of the live-in registers of the successor
+  /// blocks and pristine registers. Live out registers of the end block are the
+  /// callee saved registers.
+  void addLiveOuts(const MachineBasicBlock *MBB);
+
+  /// Like addLiveOuts() but does not add pristine registers/callee saved
+  /// registers.
+  void addLiveOutsNoPristines(const MachineBasicBlock *MBB);
 
   typedef SparseSet<unsigned>::const_iterator const_iterator;
   const_iterator begin() const { return LiveRegs.begin(); }

llvm/lib/CodeGen/ExecutionDepsFix.cpp

@@ -558,7 +558,9 @@ void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) {
 
   // Collect this block's live out register units.
   LiveRegSet.init(TRI);
-  LiveRegSet.addLiveOuts(MBB);
+  // We do not need to care about pristine registers as they are just preserved
+  // but not actually used in the function.
+  LiveRegSet.addLiveOutsNoPristines(MBB);
 
   MachineInstr *UndefMI = UndefReads.back().first;
   unsigned OpIdx = UndefReads.back().second;

llvm/lib/CodeGen/LivePhysRegs.cpp

@@ -135,22 +135,25 @@ static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) {
 /// Add pristine registers to the given \p LiveRegs. This function removes
 /// actually saved callee save registers when \p InPrologueEpilogue is false.
 static void addPristines(LivePhysRegs &LiveRegs, const MachineFunction &MF,
+                         const MachineFrameInfo &MFI,
                          const TargetRegisterInfo &TRI) {
-  const MachineFrameInfo &MFI = *MF.getFrameInfo();
-  if (!MFI.isCalleeSavedInfoValid())
-    return;
-
   for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
     LiveRegs.addReg(*CSR);
   for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
     LiveRegs.removeReg(Info.getReg());
 }
 
-void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB,
-                               bool AddPristinesAndCSRs) {
-  if (AddPristinesAndCSRs) {
-    const MachineFunction &MF = *MBB->getParent();
-    addPristines(*this, MF, *TRI);
+void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock *MBB) {
+  // To get the live-outs we simply merge the live-ins of all successors.
+  for (const MachineBasicBlock *Succ : MBB->successors())
+    ::addLiveIns(*this, *Succ);
+}
+
+void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB) {
+  const MachineFunction &MF = *MBB->getParent();
+  const MachineFrameInfo &MFI = *MF.getFrameInfo();
+  if (MFI.isCalleeSavedInfoValid()) {
+    addPristines(*this, MF, MFI, *TRI);
     if (MBB->isReturnBlock()) {
       // The return block has no successors whose live-ins we could merge
       // below. So instead we add the callee saved registers manually.
@@ -159,16 +162,13 @@ void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB,
     }
   }
 
-  // To get the live-outs we simply merge the live-ins of all successors.
-  for (const MachineBasicBlock *Succ : MBB->successors())
-    ::addLiveIns(*this, *Succ);
+  addLiveOutsNoPristines(MBB);
 }
 
-void LivePhysRegs::addLiveIns(const MachineBasicBlock *MBB,
-                              bool AddPristines) {
-  if (AddPristines) {
-    const MachineFunction &MF = *MBB->getParent();
-    addPristines(*this, MF, *TRI);
-  }
+void LivePhysRegs::addLiveIns(const MachineBasicBlock *MBB) {
+  const MachineFunction &MF = *MBB->getParent();
+  const MachineFrameInfo &MFI = *MF.getFrameInfo();
+  if (MFI.isCalleeSavedInfoValid())
+    addPristines(*this, MF, MFI, *TRI);
   ::addLiveIns(*this, *MBB);
 }

llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp

@@ -127,7 +127,8 @@ bool StackMapLiveness::calculateLiveness(MachineFunction &MF) {
   for (auto &MBB : MF) {
     DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n");
     LiveRegs.init(TRI);
-    LiveRegs.addLiveOuts(&MBB);
+    // FIXME: This should probably be addLiveOuts().
+    LiveRegs.addLiveOutsNoPristines(&MBB);
     bool HasStackMap = false;
     // Reverse iterate over all instructions and add the current live register
     // set to an instruction if we encounter a patchpoint instruction.

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

@@ -607,7 +607,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
   MachineOperand &New = MI.getOperand(4);
 
   LivePhysRegs LiveRegs(&TII->getRegisterInfo());
-  LiveRegs.addLiveOuts(&MBB, /*AddPristinesAndCSRs=*/true);
+  LiveRegs.addLiveOuts(&MBB);
   for (auto I = std::prev(MBB.end()); I != MBBI; --I)
     LiveRegs.stepBackward(*I);
 
@@ -685,7 +685,7 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
   MachineOperand &NewHi = MI.getOperand(7);
 
   LivePhysRegs LiveRegs(&TII->getRegisterInfo());
-  LiveRegs.addLiveOuts(&MBB, /*AddPristinesAndCSRs=*/true);
+  LiveRegs.addLiveOuts(&MBB);
   for (auto I = std::prev(MBB.end()); I != MBBI; --I)
     LiveRegs.stepBackward(*I);
 

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

@@ -775,7 +775,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
   MachineOperand &New = MI.getOperand(4);
 
   LivePhysRegs LiveRegs(&TII->getRegisterInfo());
-  LiveRegs.addLiveOuts(&MBB, /*AddPristinesAndCSRs=*/true);
+  LiveRegs.addLiveOuts(&MBB);
   for (auto I = std::prev(MBB.end()); I != MBBI; --I)
     LiveRegs.stepBackward(*I);
 
@@ -897,7 +897,7 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
   unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1);
 
   LivePhysRegs LiveRegs(&TII->getRegisterInfo());
-  LiveRegs.addLiveOuts(&MBB, /*AddPristinesAndCSRs=*/true);
+  LiveRegs.addLiveOuts(&MBB);
   for (auto I = std::prev(MBB.end()); I != MBBI; --I)
     LiveRegs.stepBackward(*I);
 

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

@@ -566,7 +566,7 @@ void ARMLoadStoreOpt::moveLiveRegsBefore(const MachineBasicBlock &MBB,
   // Initialize if we never queried in this block.
   if (!LiveRegsValid) {
     LiveRegs.init(TRI);
-    LiveRegs.addLiveOuts(&MBB, true);
+    LiveRegs.addLiveOuts(&MBB);
     LiveRegPos = MBB.end();
     LiveRegsValid = true;
   }

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

@@ -467,7 +467,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
   // Look for a temporary register to use.
   // First, compute the liveness information.
   LivePhysRegs UsedRegs(STI.getRegisterInfo());
-  UsedRegs.addLiveOuts(&MBB, /*AddPristines*/ true);
+  UsedRegs.addLiveOuts(&MBB);
   // The semantic of pristines changed recently and now,
   // the callee-saved registers that are touched in the function
   // are not part of the pristines set anymore.

llvm/lib/Target/X86/X86FixupBWInsts.cpp

@@ -245,7 +245,7 @@ void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
   // to update this for each instruction.
   LiveRegs.clear();
   // We run after PEI, so we need to AddPristinesAndCSRs.
-  LiveRegs.addLiveOuts(&MBB, /*AddPristinesAndCSRs=*/true);
+  LiveRegs.addLiveOuts(&MBB);
 
   for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
     MachineInstr *NewMI = nullptr;

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -4537,7 +4537,7 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     // as this is usually wrong to read an undef value.
     if (MachineBasicBlock::LQR_Unknown == LQR) {
       LivePhysRegs LPR(&getRegisterInfo());
-      LPR.addLiveOuts(&MBB, /*AddPristinesAndCSRs*/ true);
+      LPR.addLiveOuts(&MBB);
       MachineBasicBlock::iterator I = MBB.end();
       while (I != MI) {
         --I;