[Test] Add test showing miscompilation in LoopStrengthReduce on min/m…

…ax expressions (NFC) This is a test case from #62563.
llvm · May 31, 2023 · 253e3e2 · 253e3e2 · RKSimon · May 31, 2023
1 parent f1a4230
commit 253e3e2
Showing 1 changed file with 76 additions and 0 deletions.
diff --git a/llvm/test/Transforms/LoopStrengthReduce/pr62563.ll b/llvm/test/Transforms/LoopStrengthReduce/pr62563.ll
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; RUN: opt -loop-reduce -S < %s | FileCheck %s
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; XFAIL: *
+
+define void @test() {
+; CHECK-LABEL: define void @test() {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    br label [[BB3:%.*]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB3]] ], [ 159, [[BB:%.*]] ]
+; CHECK-NEXT:    [[PHI:%.*]] = phi i64 [ 158, [[BB]] ], [ [[ADD5:%.*]], [[BB3]] ]
+; CHECK-NEXT:    [[PHI4:%.*]] = phi i32 [ 0, [[BB]] ], [ [[ADD6:%.*]], [[BB3]] ]
+; CHECK-NEXT:    [[ADD5]] = add i64 [[PHI]], -4
+; CHECK-NEXT:    [[ADD6]] = add i32 [[PHI4]], 4
+; CHECK-NEXT:    [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -4
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ult i64 [[ADD5]], 7
+; CHECK-NEXT:    br i1 [[ICMP]], label [[BB7:%.*]], label [[BB3]]
+; CHECK:       bb7:
+; CHECK-NEXT:    [[UMAX7:%.*]] = call i32 @llvm.umax.i32(i32 [[LSR_IV_NEXT]], i32 10)
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[UMAX7]], [[ADD6]]
+; CHECK-NEXT:    [[UMIN6:%.*]] = call i32 @llvm.umin.i32(i32 [[LSR_IV_NEXT]], i32 11)
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[UMIN6]], [[ADD6]]
+; CHECK-NEXT:    [[SMAX5:%.*]] = call i32 @llvm.smax.i32(i32 [[LSR_IV_NEXT]], i32 10)
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[SMAX5]], [[ADD6]]
+; CHECK-NEXT:    [[SMIN4:%.*]] = call i32 @llvm.smin.i32(i32 [[LSR_IV_NEXT]], i32 10)
+; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[SMIN4]], [[ADD6]]
+; CHECK-NEXT:    call void @use.umax.res(i32 [[TMP0]])
+; CHECK-NEXT:    call void @use.umin.res(i32 [[TMP1]])
+; CHECK-NEXT:    call void @use.smax.res(i32 [[TMP2]])
+; CHECK-NEXT:    call void @use.smin.res(i32 [[TMP3]])
+; CHECK-NEXT:    ret void
+;
+bb:
+  br label %bb3
+
+bb3:                                              ; preds = %bb3, %bb
+  %phi = phi i64 [ 158, %bb ], [ %add5, %bb3 ]
+  %phi4 = phi i32 [ 0, %bb ], [ %add6, %bb3 ]
+  %add = add i64 %phi, -3
+  %trunc = trunc i64 %add to i32
+  %umax = call i32 @llvm.umax.i32(i32 %trunc, i32 10)
+  %umin = call i32 @llvm.umin.i32(i32 %trunc, i32 11)
+  %smax = call i32 @llvm.smax.i32(i32 %trunc, i32 10)
+  %smin = call i32 @llvm.smin.i32(i32 %trunc, i32 10)
+  %add5 = add i64 %phi, -4
+  %add6 = add i32 %phi4, 4
+  %icmp = icmp ult i64 %add5, 7
+  br i1 %icmp, label %bb7, label %bb3
+
+bb7:                                              ; preds = %bb3
+  %umax.res = add i32 %add6, %umax
+  %umin.res = add i32 %add6, %umin
+  %smax.res = add i32 %add6, %smax
+  %smin.res = add i32 %add6, %smin
+  call void @use.umax.res(i32 %umax.res)
+  call void @use.umin.res(i32 %umin.res)
+  call void @use.smax.res(i32 %smax.res)
+  call void @use.smin.res(i32 %smin.res)
+  ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.umax.i32(i32, i32) #0
+declare i32 @llvm.umin.i32(i32, i32) #0
+declare i32 @llvm.smax.i32(i32, i32) #0
+declare i32 @llvm.smin.i32(i32, i32) #0
+
+declare void @use.umax.res(i32)
+declare void @use.umin.res(i32)
+declare void @use.smax.res(i32)
+declare void @use.smin.res(i32)
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }