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[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases
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Add the instruction alias sgtu (register form only), two operand forms of
s[rl]l and sra, and missing single/two operand forms of dnegu/neg.

Reviewers: dsanders

Differential Revision: https://reviews.llvm.org/D22752

llvm-svn: 276736
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Simon Dardis committed Jul 26, 2016
1 parent 57d0535 commit 273fc26
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Showing 21 changed files with 182 additions and 5 deletions.
4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td
View file
Expand Up @@ -506,11 +506,11 @@ def : MipsInstAlias<"dneg $rt, $rs",
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dneg $rt",
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dnegu $rt, $rs",
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dnegu $rt",
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MICROMIPS64R6;
12 changes: 12 additions & 0 deletions llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View file
Expand Up @@ -1095,6 +1095,18 @@ let Predicates = [InMicroMips] in {
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<
"sgt $rd, $rs, $rt",
(SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<
"sgt $rs, $rt",
(SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<
"sgtu $rd, $rs, $rt",
(SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<
"sgtu $rs, $rt",
(SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"slt $rs, $rt, $imm",
(SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
simm32_relaxed:$imm), 0>;
Expand Down
5 changes: 4 additions & 1 deletion llvm/lib/Target/Mips/Mips64InstrInfo.td
View file
Expand Up @@ -668,11 +668,14 @@ let AdditionalPredicates = [NotInMicroMips] in {
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dneg $rt",
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dnegu $rt, $rs",
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dnegu $rt",
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
ISA_MIPS3;
}
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
Expand Down
24 changes: 22 additions & 2 deletions llvm/lib/Target/Mips/MipsInstrInfo.td
View file
Expand Up @@ -2233,11 +2233,25 @@ def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
def : MipsInstAlias<"neg $rt, $rs",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"neg $rt",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
def : MipsInstAlias<"negu $rt, $rs",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<
"sgt $rd, $rs, $rt",
(SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<
"sgt $rs, $rt",
(SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<
"sgtu $rd, $rs, $rt",
(SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<
"sgtu $$rs, $rt",
(SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<
"slt $rs, $rt, $imm",
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
Expand Down Expand Up @@ -2324,6 +2338,12 @@ let AdditionalPredicates = [NotInMicroMips] in {
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sll $rd, $rt",
(SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"sra $rd, $rt",
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"srl $rd, $rt",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
}
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync",
Expand Down
5 changes: 5 additions & 0 deletions llvm/test/MC/Mips/micromips32r6/valid.s
View file
Expand Up @@ -86,6 +86,11 @@
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0x85,0x20,0x90]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x50]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
Expand Down
5 changes: 5 additions & 0 deletions llvm/test/MC/Mips/micromips64r6/valid.s
View file
Expand Up @@ -47,6 +47,11 @@ a:
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0x85,0x20,0x90]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x50]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
Expand Down
9 changes: 9 additions & 0 deletions llvm/test/MC/Mips/mips1/valid.s
View file
Expand Up @@ -77,6 +77,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
Expand All @@ -86,7 +88,12 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
sb $s6,-19857($14)
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
Expand All @@ -96,10 +103,12 @@ a:
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Expand Down
9 changes: 9 additions & 0 deletions llvm/test/MC/Mips/mips2/valid.s
View file
Expand Up @@ -97,6 +97,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
Expand All @@ -112,6 +114,11 @@ a:
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdc3 $12,5835($10)
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
Expand All @@ -124,10 +131,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Expand Down
9 changes: 9 additions & 0 deletions llvm/test/MC/Mips/mips3/valid.s
View file
Expand Up @@ -157,6 +157,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
Expand All @@ -177,7 +179,12 @@ a:
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
Expand All @@ -189,10 +196,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Expand Down
9 changes: 9 additions & 0 deletions llvm/test/MC/Mips/mips32/valid.s
View file
Expand Up @@ -125,6 +125,8 @@ a:
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
Expand All @@ -142,7 +144,12 @@ a:
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
Expand All @@ -154,10 +161,12 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
Expand Down

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