[RISCV] Bump vector crypto to v1.0 RC2

Differential Revision: https://reviews.llvm.org/D158067
llvm · Aug 18, 2023 · 29f11e4 · 29f11e4
1 parent 09e12d1
commit 29f11e4
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diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
@@ -2874,16 +2874,18 @@ multiclass RVVSignedWidenBinBuiltinSetVwsll
                           ["vx", "Uw", "UwUvz"]]>;
 
 let UnMaskedPolicyScheme = HasPassthruOperand in {
-  // zvbb
+  // zvkb
   defm vandn   : RVVUnsignedBinBuiltinSet;
-  defm vbrev   : RVVOutBuiltinSetZvbb;
   defm vbrev8  : RVVOutBuiltinSetZvbb;
   defm vrev8   : RVVOutBuiltinSetZvbb;
+  defm vrol    : RVVUnsignedShiftBuiltinSet;
+  defm vror    : RVVUnsignedShiftBuiltinSet;
+
+  // zvbb
+  defm vbrev   : RVVOutBuiltinSetZvbb;
   defm vclz    : RVVOutBuiltinSetZvbb;
   defm vctz    : RVVOutBuiltinSetZvbb;
   defm vcpopv  : RVVOutBuiltinSetZvbb;
-  defm vrol    : RVVUnsignedShiftBuiltinSet;
-  defm vror    : RVVUnsignedShiftBuiltinSet;
   let OverloadedName = "vwsll" in
   defm vwsll   : RVVSignedWidenBinBuiltinSetVwsll;
 

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
@@ -3,6 +3,7 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
 // RUN:   -target-feature +experimental-zvbb \
 // RUN:   -target-feature +experimental-zvbc \
+// RUN:   -target-feature +experimental-zvkb \
 // RUN:   -target-feature +experimental-zvkg \
 // RUN:   -target-feature +experimental-zvkned \
 // RUN:   -target-feature +experimental-zvknhb \

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
@@ -211,8 +211,8 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-ztso``
   LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25).  The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document.  There are multiple possible mappings, and they are *not* mutually ABI compatible.  The mapping LLVM implements is ABI compatible with the default WMO mapping.  This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status.  User beware.
 
-``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
-  LLVM implements the `1.0.0-rc1 specification <https://github.com/riscv/riscv-crypto/releases/download/v20230620/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
+``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
+  LLVM implements the `1.0.0-rc2 specification <https://github.com/riscv/riscv-crypto/releases/download/v/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
 
 To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using.  To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`.  Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
 

diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1830,16 +1830,18 @@ def int_riscv_sm3p1      : ScalarCryptoGprIntrinsic32;
 // These intrinsics will lower directly into the corresponding instructions
 // added by the vector cyptography extension, if the extension is present.
 let TargetPrefix = "riscv" in {
-  // Zvbb
+  // Zvkb
   defm vandn             : RISCVBinaryAAX;
-  defm vbrev             : RISCVUnaryAA;
   defm vbrev8            : RISCVUnaryAA;
   defm vrev8             : RISCVUnaryAA;
+  defm vrol              : RISCVBinaryAAX;
+  defm vror              : RISCVBinaryAAX;
+
+  // Zvbb
+  defm vbrev             : RISCVUnaryAA;
   defm vclz              : RISCVUnaryAA;
   defm vctz              : RISCVUnaryAA;
   defm vcpopv            : RISCVUnaryAA;
-  defm vrol              : RISCVBinaryAAX;
-  defm vror              : RISCVBinaryAAX;
   defm vwsll             : RISCVBinaryABX;
 
   // Zvbc

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -180,6 +180,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zvfbfwma", RISCVExtensionVersion{0, 8}},
 
     // vector crypto
+    {"zvkb", RISCVExtensionVersion{1, 0}},
     {"zvkg", RISCVExtensionVersion{1, 0}},
     {"zvkn", RISCVExtensionVersion{1, 0}},
     {"zvknc", RISCVExtensionVersion{1, 0}},
@@ -975,6 +976,7 @@ static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
                                        "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
+static const char *ImpliedExtsZvbb[] = {"zvkb"};
 static const char *ImpliedExtsZve32f[] = {"zve32x", "f"};
 static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
 static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
@@ -983,11 +985,11 @@ static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
 static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"};
 static const char *ImpliedExtsZvfbfwma[] = {"zvfbfmin"};
 static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
-static const char *ImpliedExtsZvkn[] = {"zvbb", "zvkned", "zvknhb", "zvkt"};
+static const char *ImpliedExtsZvkn[] = {"zvkb", "zvkned", "zvknhb", "zvkt"};
 static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
 static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
 static const char *ImpliedExtsZvknhb[] = {"zvknha"};
-static const char *ImpliedExtsZvks[] = {"zvbb", "zvksed", "zvksh", "zvkt"};
+static const char *ImpliedExtsZvks[] = {"zvkb", "zvksed", "zvksh", "zvkt"};
 static const char *ImpliedExtsZvksc[] = {"zvbc", "zvks"};
 static const char *ImpliedExtsZvksg[] = {"zvkg", "zvks"};
 static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
@@ -1040,6 +1042,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"zk"}, {ImpliedExtsZk}},
     {{"zkn"}, {ImpliedExtsZkn}},
     {{"zks"}, {ImpliedExtsZks}},
+    {{"zvbb"}, {ImpliedExtsZvbb}},
     {{"zve32f"}, {ImpliedExtsZve32f}},
     {{"zve32x"}, {ImpliedExtsZve32x}},
     {{"zve64d"}, {ImpliedExtsZve64d}},

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -550,12 +550,20 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
                                AssemblerPredicate<(all_of FeatureStdExtZawrs),
                                "'Zawrs' (Wait on Reservation Set)">;
 
+def FeatureStdExtZvkb
+    : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
+                       "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
+def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
+                              AssemblerPredicate<(all_of FeatureStdExtZvkb),
+                              "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
+
 def FeatureStdExtZvbb
     : SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
-                       "'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
+                       "'Zvbb' (Vector basic bit-manipulation instructions.)",
+                       [FeatureStdExtZvkb]>;
 def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
                               AssemblerPredicate<(all_of FeatureStdExtZvbb),
-                              "'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
+                              "'Zvbb' (Vector basic bit-manipulation instructions.)">;
 
 def FeatureStdExtZvbc
     : SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
@@ -613,9 +621,9 @@ def FeatureStdExtZvkt
 def FeatureStdExtZvkn
     : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
                        "This extension is shorthand for the following set of "
-                       "other extensions: Zvkned, Zvknhb, Zvbb and Zvkt.",
+                       "other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
                        [FeatureStdExtZvkned, FeatureStdExtZvknhb,
-                        FeatureStdExtZvbb, FeatureStdExtZvkt]>;
+                        FeatureStdExtZvkb, FeatureStdExtZvkt]>;
 
 def FeatureStdExtZvknc
     : SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
@@ -632,9 +640,9 @@ def FeatureStdExtZvkng
 def FeatureStdExtZvks
     : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
                        "This extension is shorthand for the following set of "
-                       "other extensions: Zvksed, Zvksh, Zvbb and Zvkt.",
+                       "other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
                        [FeatureStdExtZvksed, FeatureStdExtZvksh,
-                        FeatureStdExtZvbb, FeatureStdExtZvkt]>;
+                        FeatureStdExtZvkb, FeatureStdExtZvkt]>;
 
 def FeatureStdExtZvksc
     : SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",