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[MachineDebugify] Insert synthetic DBG_VALUE instructions
Summary: Teach MachineDebugify how to insert DBG_VALUE instructions. This can help find bugs causing CodeGen differences when debug info is present. DBG_VALUE instructions are only emitted when -debugify-level is set to locations+variables. There is essentially no attempt made to match up DBG_VALUE register operands with the local variables they ought to correspond to. I'm not sure how to improve the situation. In some cases (MachineMemOperand?) it's possible to find the IR instruction a MachineInstr corresponds to, but in general this seems to call for "undoing" the work done by ISel. Reviewers: dsanders, aprantl Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78135
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33 changes: 33 additions & 0 deletions
33
llvm/test/CodeGen/AArch64/GlobalISel/constant-mir-debugify.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | ||
# RUN: llc -debugify-and-strip-all-safe=0 -run-pass=mir-debugify -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s | ||
... | ||
--- | ||
name: fconstant_to_constant_s32 | ||
alignment: 4 | ||
tracksRegLiveness: true | ||
frameInfo: | ||
maxAlignment: 1 | ||
machineFunctionInfo: {} | ||
body: | | ||
bb.0: | ||
liveins: $x0 | ||
; CHECK-LABEL: name: fconstant_to_constant_s32 | ||
; CHECK: liveins: $x0 | ||
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0, debug-location !10 | ||
; CHECK: DBG_VALUE [[COPY]](p0), $noreg, !8, !DIExpression(), debug-location !10 | ||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FA99999A0000000, debug-location !DILocation(line: 2, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[C]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5) | ||
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 524, debug-location !DILocation(line: 3, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[C1]](s64), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 3, column: 1, scope: !5) | ||
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64), debug-location !DILocation(line: 4, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[PTR_ADD]](p0), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5) | ||
; CHECK: G_STORE [[C]](s32), [[PTR_ADD]](p0), debug-location !DILocation(line: 5, column: 1, scope: !5) :: (store 4) | ||
; CHECK: DBG_VALUE 0, $noreg, !8, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5) | ||
; CHECK: RET_ReallyLR debug-location !DILocation(line: 6, column: 1, scope: !5) | ||
%0:_(p0) = COPY $x0 | ||
%3:_(s32) = G_FCONSTANT float 0x3FA99999A0000000 | ||
%1:_(s64) = G_CONSTANT i64 524 | ||
%2:_(p0) = G_PTR_ADD %0, %1(s64) | ||
G_STORE %3(s32), %2(p0) :: (store 4) | ||
RET_ReallyLR | ||
... |
2 changes: 1 addition & 1 deletion
2
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
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106 changes: 106 additions & 0 deletions
106
llvm/test/CodeGen/AArch64/GlobalISel/phi-mir-debugify.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | ||
# RUN: llc -debugify-and-strip-all-safe=0 -run-pass=mir-debugify -verify-machineinstrs %s -o - | FileCheck %s | ||
--- | | ||
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" | ||
target triple = "aarch64-unknown-unknown" | ||
|
||
define i32 @legalize_phi(i32 %argc) { | ||
entry: | ||
ret i32 0 | ||
} | ||
|
||
... | ||
--- | ||
name: legalize_phi | ||
alignment: 4 | ||
exposesReturnsTwice: false | ||
legalized: false | ||
regBankSelected: false | ||
selected: false | ||
tracksRegLiveness: true | ||
registers: | ||
- { id: 0, class: _, preferred-register: '' } | ||
- { id: 1, class: _, preferred-register: '' } | ||
- { id: 2, class: _, preferred-register: '' } | ||
- { id: 3, class: _, preferred-register: '' } | ||
- { id: 4, class: _, preferred-register: '' } | ||
- { id: 5, class: _, preferred-register: '' } | ||
- { id: 6, class: _, preferred-register: '' } | ||
- { id: 7, class: _, preferred-register: '' } | ||
- { id: 8, class: _, preferred-register: '' } | ||
- { id: 9, class: _, preferred-register: '' } | ||
- { id: 10, class: _, preferred-register: '' } | ||
liveins: | ||
body: | | ||
; CHECK-LABEL: name: legalize_phi | ||
; CHECK: bb.0: | ||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) | ||
; CHECK: liveins: $w0 | ||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0, debug-location !10 | ||
; CHECK: DBG_VALUE [[COPY]](s32), $noreg, !8, !DIExpression(), debug-location !10 | ||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0, debug-location !DILocation(line: 2, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[C]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5) | ||
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1, debug-location !DILocation(line: 3, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[C1]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 3, column: 1, scope: !5) | ||
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2, debug-location !DILocation(line: 4, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[C2]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5) | ||
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]], debug-location !DILocation(line: 5, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[ICMP]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5) | ||
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1, debug-location !DILocation(line: 6, column: 1, scope: !5) | ||
; CHECK: G_BR %bb.2, debug-location !DILocation(line: 7, column: 1, scope: !5) | ||
; CHECK: bb.1: | ||
; CHECK: successors: %bb.3(0x80000000) | ||
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]], debug-location !DILocation(line: 8, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[ADD]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 8, column: 1, scope: !5) | ||
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ADD]](s32), debug-location !DILocation(line: 9, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[TRUNC]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 9, column: 1, scope: !5) | ||
; CHECK: G_BR %bb.3, debug-location !DILocation(line: 10, column: 1, scope: !5) | ||
; CHECK: bb.2: | ||
; CHECK: successors: %bb.3(0x80000000) | ||
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]], debug-location !DILocation(line: 11, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[ADD1]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 11, column: 1, scope: !5) | ||
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ADD1]](s32), debug-location !DILocation(line: 12, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[TRUNC1]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 12, column: 1, scope: !5) | ||
; CHECK: bb.3: | ||
; CHECK: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.1, [[TRUNC1]](s1), %bb.2, debug-location !DILocation(line: 13, column: 1, scope: !5) | ||
; CHECK: [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.1, [[TRUNC1]](s1), %bb.2, debug-location !DILocation(line: 14, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[PHI]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 13, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[PHI1]](s1), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 14, column: 1, scope: !5) | ||
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[PHI]](s1), debug-location !DILocation(line: 15, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE [[ZEXT]](s32), $noreg, !8, !DIExpression(), debug-location !DILocation(line: 15, column: 1, scope: !5) | ||
; CHECK: $w0 = COPY [[ZEXT]](s32), debug-location !DILocation(line: 16, column: 1, scope: !5) | ||
; CHECK: DBG_VALUE $w0, $noreg, !8, !DIExpression(), debug-location !DILocation(line: 16, column: 1, scope: !5) | ||
; CHECK: RET_ReallyLR implicit $w0, debug-location !DILocation(line: 17, column: 1, scope: !5) | ||
bb.0: | ||
successors: %bb.1(0x40000000), %bb.2(0x40000000) | ||
liveins: $w0 | ||
%0(s32) = COPY $w0 | ||
%1(s32) = G_CONSTANT i32 0 | ||
%3(s32) = G_CONSTANT i32 1 | ||
%6(s32) = G_CONSTANT i32 2 | ||
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1 | ||
G_BRCOND %2(s1), %bb.1 | ||
G_BR %bb.2 | ||
bb.1: | ||
successors: %bb.3(0x80000000) | ||
%4(s32) = G_ADD %0, %3 | ||
%5(s1) = G_TRUNC %4(s32) | ||
G_BR %bb.3 | ||
bb.2: | ||
successors: %bb.3(0x80000000) | ||
%7(s32) = G_ADD %0, %6 | ||
%8(s1) = G_TRUNC %7(s32) | ||
bb.3: | ||
%9(s1) = G_PHI %5(s1), %bb.1, %8(s1), %bb.2 | ||
%11:_(s1) = G_PHI %5(s1), %bb.1, %8(s1), %bb.2 | ||
%10(s32) = G_ZEXT %9(s1) | ||
$w0 = COPY %10(s32) | ||
RET_ReallyLR implicit $w0 | ||
... |
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