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[ARM] Rename v8.1a from "extension" to "architecture"
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v8.1a is renamed to architecture, following current entity naming approach.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8767

llvm-svn: 233811
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Vladimir Sukharev committed Apr 1, 2015
1 parent 439328e commit 2afdb32
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Showing 7 changed files with 26 additions and 36 deletions.
10 changes: 1 addition & 9 deletions llvm/lib/Target/ARM/ARM.td
View file
Expand Up @@ -175,7 +175,7 @@ def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
"Support ARM v8 instructions",
[HasV7Ops, FeatureVirtualization,
FeatureMP]>;
def FeatureV8_1a : SubtargetFeature<"v8.1a", "HasV8_1a", "true",
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
"Support ARM v8.1a instructions",
[HasV8Ops, FeatureAClass, FeatureCRC]>;

Expand Down Expand Up @@ -452,14 +452,6 @@ def : ProcessorModel<"cyclone", SwiftModel,
FeatureDB,FeatureDSPThumb2,
FeatureHasRAS, FeatureZCZeroing]>;

// V8.1 Processors
def : ProcNoItin<"generic-armv8.1-a", [HasV8Ops, FeatureV8_1a,
FeatureDB, FeatureFPARMv8,
FeatureNEON, FeatureDSPThumb2,
FeatureHWDiv, FeatureHWDivARM,
FeatureTrustZone, FeatureT2XtPk,
FeatureCrypto]>;

//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMAsmPrinter.cpp
View file
Expand Up @@ -661,8 +661,8 @@ void ARMAsmPrinter::emitAttributes() {
// Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
if (STI.hasV8Ops())
ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
STI.hasV8_1a() ? ARMBuildAttrs::AllowNeonARMv8_1a:
ARMBuildAttrs::AllowNeonARMv8);
STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
ARMBuildAttrs::AllowNeonARMv8);
} else {
if (STI.hasFPARMv8())
// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMInstrInfo.td
View file
Expand Up @@ -208,6 +208,8 @@ def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
AssemblerPredicate<"HasV8Ops", "armv8">;
def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
AssemblerPredicate<"FeatureVFP2", "VFP2">;
Expand All @@ -226,8 +228,6 @@ def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
AssemblerPredicate<"FeatureCrypto", "crypto">;
def HasCRC : Predicate<"Subtarget->hasCRC()">,
AssemblerPredicate<"FeatureCRC", "crc">;
def HasV8_1a : Predicate<"Subtarget->hasV8_1a()">,
AssemblerPredicate<"FeatureV8_1a", "v8.1a">;
def HasFP16 : Predicate<"Subtarget->hasFP16()">,
AssemblerPredicate<"FeatureFP16","half-float">;
def HasDivide : Predicate<"Subtarget->hasDivide()">,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMSubtarget.cpp
View file
Expand Up @@ -133,6 +133,7 @@ void ARMSubtarget::initializeEnvironment() {
HasV6T2Ops = false;
HasV7Ops = false;
HasV8Ops = false;
HasV8_1aOps = false;
HasVFPv2 = false;
HasVFPv3 = false;
HasVFPv4 = false;
Expand Down Expand Up @@ -166,7 +167,6 @@ void ARMSubtarget::initializeEnvironment() {
HasTrustZone = false;
HasCrypto = false;
HasCRC = false;
HasV8_1a = false;
HasZeroCycleZeroing = false;
AllowsUnalignedMem = false;
Thumb2DSP = false;
Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/Target/ARM/ARMSubtarget.h
View file
Expand Up @@ -67,6 +67,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool HasV6T2Ops;
bool HasV7Ops;
bool HasV8Ops;
bool HasV8_1aOps;

/// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
/// floating point ISAs are supported.
Expand Down Expand Up @@ -182,9 +183,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
/// HasCRC - if true, processor supports CRC instructions
bool HasCRC;

/// HasV8_1a - if true, the processor has V8.1a: PAN and RDMA extensions
bool HasV8_1a;

/// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
/// particularly effective at zeroing a VFP register.
bool HasZeroCycleZeroing;
Expand Down Expand Up @@ -292,6 +290,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool hasV6T2Ops() const { return HasV6T2Ops; }
bool hasV7Ops() const { return HasV7Ops; }
bool hasV8Ops() const { return HasV8Ops; }
bool hasV8_1aOps() const { return HasV8_1aOps; }

bool isCortexA5() const { return ARMProcFamily == CortexA5; }
bool isCortexA7() const { return ARMProcFamily == CortexA7; }
Expand All @@ -313,7 +312,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
bool hasCRC() const { return HasCRC; }
bool hasV8_1a() const { return HasV8_1a; }
bool hasVirtualization() const { return HasVirtualization; }
bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View file
Expand Up @@ -276,8 +276,8 @@ class ARMAsmParser : public MCTargetAsmParser {
bool hasD16() const {
return STI.getFeatureBits() & ARM::FeatureD16;
}
bool hasV8_1a() const {
return STI.getFeatureBits() & ARM::FeatureV8_1a;
bool hasV8_1aOps() const {
return STI.getFeatureBits() & ARM::HasV8_1aOps;
}

void SwitchMode() {
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s
View file
Expand Up @@ -43,57 +43,57 @@
vqrdmlah.s16 d0, d1, d2
//CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0b]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 d0, d1, d2
//CHECK-V8: ^

vqrdmlah.s32 d0, d1, d2
//CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x12,0x0b,0x21,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0b]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 d0, d1, d2
//CHECK-V8: ^

vqrdmlah.s16 q0, q1, q2
//CHECK-V81aARM: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x54,0x0b,0x12,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0b]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 q0, q1, q2
//CHECK-V8: ^

vqrdmlah.s32 q2, q3, q0
//CHECK-V81aARM: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x50,0x4b,0x26,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s32 q2, q3, q0 @ encoding: [0x26,0xff,0x50,0x4b]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 q2, q3, q0
//CHECK-V8: ^


vqrdmlsh.s16 d7, d6, d5
//CHECK-V81aARM: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x15,0x7c,0x16,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x16,0xff,0x15,0x7c]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 d7, d6, d5
//CHECK-V8: ^

vqrdmlsh.s32 d0, d1, d2
//CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x12,0x0c,0x21,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2 @ encoding: [0x21,0xff,0x12,0x0c]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 d0, d1, d2
//CHECK-V8: ^

vqrdmlsh.s16 q0, q1, q2
//CHECK-V81aARM: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x54,0x0c,0x12,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0c]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 q0, q1, q2
//CHECK-V8: ^

vqrdmlsh.s32 q3, q4, q5
//CHECK-V81aARM: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x5a,0x6c,0x28,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s32 q3, q4, q5 @ encoding: [0x28,0xff,0x5a,0x6c]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 q3, q4, q5
//CHECK-V8: ^

Expand All @@ -119,56 +119,56 @@
vqrdmlah.s16 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x42,0x0e,0x91,0xf2]
//CHECK-V81aTHUMB: vqrdmlah.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0e]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 d0, d1, d2[0]
//CHECK-V8: ^

vqrdmlah.s32 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0x42,0x0e,0xa1,0xf2]
//CHECK-V81aTHUMB: vqrdmlah.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0e]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 d0, d1, d2[0]
//CHECK-V8: ^

vqrdmlah.s16 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x42,0x0e,0x92,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0e]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s16 q0, q1, d2[0]
//CHECK-V8: ^

vqrdmlah.s32 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0x42,0x0e,0xa2,0xf3]
//CHECK-V81aTHUMB: vqrdmlah.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0e]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlah.s32 q0, q1, d2[0]
//CHECK-V8: ^


vqrdmlsh.s16 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x42,0x0f,0x91,0xf2]
//CHECK-V81aTHUMB: vqrdmlsh.s16 d0, d1, d2[0] @ encoding: [0x91,0xef,0x42,0x0f]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 d0, d1, d2[0]
//CHECK-V8: ^

vqrdmlsh.s32 d0, d1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0x42,0x0f,0xa1,0xf2]
//CHECK-V81aTHUMB: vqrdmlsh.s32 d0, d1, d2[0] @ encoding: [0xa1,0xef,0x42,0x0f]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 d0, d1, d2[0]
//CHECK-V8: ^

vqrdmlsh.s16 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x42,0x0f,0x92,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s16 q0, q1, d2[0] @ encoding: [0x92,0xff,0x42,0x0f]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s16 q0, q1, d2[0]
//CHECK-V8: ^

vqrdmlsh.s32 q0, q1, d2[0]
//CHECK-V81aARM: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0x42,0x0f,0xa2,0xf3]
//CHECK-V81aTHUMB: vqrdmlsh.s32 q0, q1, d2[0] @ encoding: [0xa2,0xff,0x42,0x0f]
//CHECK-V8: error: instruction requires: v8.1a
//CHECK-V8: error: instruction requires: armv8.1a
//CHECK-V8: vqrdmlsh.s32 q0, q1, d2[0]
//CHECK-V8: ^

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