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[mips][msa] Mask vectors holding shift amounts
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Masked vectors which hold shift amounts when creating the following nodes:
ISD::SHL, ISD::SRL or ISD::SRA.
Instructions that use said nodes, which have had their arguments altered are
sll, srl, sra, bneg, bclr and bset.

For said instructions, the shift amount or the bit position that is
specified in the corresponding vector elements will be interpreted as the
shift amount/bit position modulo the size of the element in bits.

The problem lies in compiling with -O2 enabled, where the instructions for
formats .w and .d are not generated, but are instead optimized away.
In this case, having shift amounts that are either negative or greater than
the element bit size results in generation of incorrect results when
constant folding.

We remedy this by masking the operands for the nodes mentioned above before
actually creating them, so that the final result is correct before placed
into the constant pool.

Patch by Stefan Maksimovic.

Differential Revision: https://reviews.llvm.org/D31331

llvm-svn: 300839
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@petar-jovanovic
petar-jovanovic committed Apr 20, 2017
1 parent 5054782 commit 2b6fe3f
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74 changes: 74 additions & 0 deletions llvm/lib/Target/Mips/MipsMSAInstrInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3781,6 +3781,80 @@ let Predicates = [HasMSA] in {
ISA_MIPS1_NOT_32R6_64R6;
}

def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
APInt Imm;
SDNode *BV = N->getOperand(0).getNode();
EVT EltTy = N->getValueType(0).getVectorElementType();

return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
}]>;

def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>;
def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>;
def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>;

def vsplati8imm7 : PatFrag<(ops node:$wt),
(and node:$wt, (vsplati8 immi32Cst7))>;
def vsplati16imm15 : PatFrag<(ops node:$wt),
(and node:$wt, (vsplati16 immi32Cst15))>;
def vsplati32imm31 : PatFrag<(ops node:$wt),
(and node:$wt, (vsplati32 immi32Cst31))>;
def vsplati64imm63 : PatFrag<(ops node:$wt),
(and node:$wt, vsplati64_imm_eq_63)>;

class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> :
MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))),
(VT (Insn VT:$ws, VT:$wt))>;

class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> :
MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))),
(VT (Insn VT:$ws, VT:$wt))>;

multiclass MSAShiftPats<SDNode Node, string Insn> {
def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B),
(vsplati8 immi32Cst7)>;
def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H),
(vsplati16 immi32Cst15)>;
def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W),
(vsplati32 immi32Cst31)>;
def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt,
vsplati64_imm_eq_63)))),
(v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
}

multiclass MSABitPats<SDNode Node, string Insn> {
def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>;
def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>;
def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>;
def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1),
(vsplati64imm63 v2i64:$wt))),
(v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
}

defm : MSAShiftPats<shl, "SLL">;
defm : MSAShiftPats<srl, "SRL">;
defm : MSAShiftPats<sra, "SRA">;
defm : MSABitPats<xor, "BNEG">;
defm : MSABitPats<or, "BSET">;

def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1,
(vsplati8imm7 v16i8:$wt)),
immAllOnesV)),
(v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>;
def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1,
(vsplati16imm15 v8i16:$wt)),
immAllOnesV)),
(v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>;
def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1,
(vsplati32imm31 v4i32:$wt)),
immAllOnesV)),
(v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>;
def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
(vsplati64imm63 v2i64:$wt)),
(bitconvert (v4i32 immAllOnesV)))),
(v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>;

// Vector extraction with fixed index.
//
// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
Expand Down
25 changes: 19 additions & 6 deletions llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1547,11 +1547,24 @@ static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
}

static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG) {
SDLoc DL(Op);
EVT ResTy = Op->getValueType(0);
SDValue Vec = Op->getOperand(2);
bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
DL, ResEltTy);
SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);

return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
}

static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
EVT ResTy = Op->getValueType(0);
SDLoc DL(Op);
SDValue One = DAG.getConstant(1, DL, ResTy);
SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));

return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
DAG.getNOT(DL, Bit, ResTy));
Expand Down Expand Up @@ -1687,7 +1700,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,

return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One,
Op->getOperand(2)));
truncateVecElts(Op, DAG)));
}
case Intrinsic::mips_bnegi_b:
case Intrinsic::mips_bnegi_h:
Expand Down Expand Up @@ -1723,7 +1736,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,

return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One,
Op->getOperand(2)));
truncateVecElts(Op, DAG)));
}
case Intrinsic::mips_bseti_b:
case Intrinsic::mips_bseti_h:
Expand Down Expand Up @@ -2210,7 +2223,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_sll_w:
case Intrinsic::mips_sll_d:
return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
truncateVecElts(Op, DAG));
case Intrinsic::mips_slli_b:
case Intrinsic::mips_slli_h:
case Intrinsic::mips_slli_w:
Expand Down Expand Up @@ -2240,7 +2253,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_sra_w:
case Intrinsic::mips_sra_d:
return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
truncateVecElts(Op, DAG));
case Intrinsic::mips_srai_b:
case Intrinsic::mips_srai_h:
case Intrinsic::mips_srai_w:
Expand Down Expand Up @@ -2270,7 +2283,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_srl_w:
case Intrinsic::mips_srl_d:
return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
truncateVecElts(Op, DAG));
case Intrinsic::mips_srli_b:
case Intrinsic::mips_srli_h:
case Intrinsic::mips_srli_w:
Expand Down
171 changes: 171 additions & 0 deletions llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,171 @@
; Test whether the following functions, with vectors featuring negative or values larger than the element
; bit size have their results of operations generated correctly when placed into constant pools

; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64 %s
; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32 %s
; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64 %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32 %s

@llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16

define void @llvm_mips_bclr_w_test_const_vec() nounwind {
entry:
%0 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> <i32 2147483649, i32 2147483649, i32 7, i32 7>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)
store <4 x i32> %0, <4 x i32>* @llvm_mips_bclr_w_test_const_vec_res
ret void
}

declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind

; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:
; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:
; ALL: .4byte 1 # 0x1
; ALL: .4byte 1 # 0x1
; ALL: .4byte 3 # 0x3
; ALL: .4byte 3 # 0x3
; ALL-LABEL: llvm_mips_bclr_w_test_const_vec:
; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])
; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])
; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bclr_w_test_const_vec_res)($[[R1]])
; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])
; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])
; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_bclr_w_test_const_vec_res)($[[R1]])
; ALL: ld.w $w0, 0($[[R2]])
; ALL: st.w $w0, 0($[[R3]])


@llvm_mips_bneg_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16

define void @llvm_mips_bneg_w_test_const_vec() nounwind {
entry:
%0 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> <i32 2147483649, i32 2147483649, i32 7, i32 7>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)
store <4 x i32> %0, <4 x i32>* @llvm_mips_bneg_w_test_const_vec_res
ret void
}

declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind

; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:
; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:
; ALL: .4byte 1 # 0x1
; ALL: .4byte 1 # 0x1
; ALL: .4byte 3 # 0x3
; ALL: .4byte 3 # 0x3
; ALL-LABEL: llvm_mips_bneg_w_test_const_vec:
; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])
; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])
; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bneg_w_test_const_vec_res)($[[R1]])
; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])
; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])
; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_bneg_w_test_const_vec_res)($[[R1]])
; ALL: ld.w $w0, 0($[[R2]])
; ALL: st.w $w0, 0($[[R3]])


@llvm_mips_bset_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16

define void @llvm_mips_bset_w_test_const_vec() nounwind {
entry:
%0 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)
store <4 x i32> %0, <4 x i32>* @llvm_mips_bset_w_test_const_vec_res
ret void
}

declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind

; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:
; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:
; ALL: .4byte 2147483648 # 0x80000000
; ALL: .4byte 2147483648 # 0x80000000
; ALL: .4byte 4 # 0x4
; ALL: .4byte 4 # 0x4
; ALL-LABEL: llvm_mips_bset_w_test_const_vec:
; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])
; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])
; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bset_w_test_const_vec_res)($[[R1]])
; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])
; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])
; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_bset_w_test_const_vec_res)($[[R1]])
; ALL: ld.w $w0, 0($[[R2]])
; ALL: st.w $w0, 0($[[R3]])

@llvm_mips_sll_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16

define void @llvm_mips_sll_w_test_const_vec() nounwind {
entry:
%0 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 31, i32 2, i32 34>)
store <4 x i32> %0, <4 x i32>* @llvm_mips_sll_w_test_const_vec_res
ret void
}

declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind

; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:
; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:
; ALL: .4byte 2147483648 # 0x80000000
; ALL: .4byte 2147483648 # 0x80000000
; ALL: .4byte 4 # 0x4
; ALL: .4byte 4 # 0x4
; ALL-LABEL: llvm_mips_sll_w_test_const_vec:
; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])
; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])
; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sll_w_test_const_vec_res)($[[R1]])
; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])
; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])
; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_sll_w_test_const_vec_res)($[[R1]])
; ALL: ld.w $w0, 0($[[R2]])
; ALL: st.w $w0, 0($[[R3]])

@llvm_mips_sra_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16

define void @llvm_mips_sra_w_test_const_vec() nounwind {
entry:
%0 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> <i32 -16, i32 16, i32 16, i32 16>, <4 x i32> <i32 2, i32 -30, i32 33, i32 1>)
store <4 x i32> %0, <4 x i32>* @llvm_mips_sra_w_test_const_vec_res
ret void
}

declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind

; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:
; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:
; ALL: .4byte 4294967292 # 0xfffffffc
; ALL: .4byte 4 # 0x4
; ALL: .4byte 8 # 0x8
; ALL: .4byte 8 # 0x8
; ALL-LABEL: llvm_mips_sra_w_test_const_vec:
; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])
; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])
; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sra_w_test_const_vec_res)($[[R1]])
; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])
; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])
; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_sra_w_test_const_vec_res)($[[R1]])
; ALL: ld.w $w0, 0($[[R2]])
; ALL: st.w $w0, 0($[[R3]])

@llvm_mips_srl_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16

define void @llvm_mips_srl_w_test_const_vec() nounwind {
entry:
%0 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> <i32 -16, i32 16, i32 16, i32 16>, <4 x i32> <i32 2, i32 -30, i32 33, i32 1>)
store <4 x i32> %0, <4 x i32>* @llvm_mips_srl_w_test_const_vec_res
ret void
}

declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind

; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]:
; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]:
; ALL: .4byte 1073741820 # 0x3ffffffc
; ALL: .4byte 4 # 0x4
; ALL: .4byte 8 # 0x8
; ALL: .4byte 8 # 0x8
; ALL-LABEL: llvm_mips_srl_w_test_const_vec:
; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]])
; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]])
; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_srl_w_test_const_vec_res)($[[R1]])
; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]])
; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]])
; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_srl_w_test_const_vec_res)($[[R1]])
; ALL: ld.w $w0, 0($[[R2]])
; ALL: st.w $w0, 0($[[R3]])

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