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Add baseline tests for D147404
Differential Revision: https://reviews.llvm.org/D147409 Signed-off-by: Jun Zhang <jun@junz.org>
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‎llvm/test/CodeGen/AArch64/hadd-combine.ll‎

Lines changed: 241 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,7 @@ define <8 x i16> @hadds_const_both() {
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define <8 x i16> @hadds_const_bothhigh() {
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; CHECK-LABEL: hadds_const_bothhigh:
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; CHECK: // %bb.0:
237-
; CHECK-NEXT: mov w8, #32766
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; CHECK-NEXT: mov w8, #32766 // =0x7ffe
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; CHECK-NEXT: dup v0.8h, w8
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; CHECK-NEXT: ret
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%ext1 = sext <8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766> to <8 x i32>
@@ -313,7 +313,7 @@ define <8 x i16> @hadds_i_const_both() {
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define <8 x i16> @hadds_i_const_bothhigh() {
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; CHECK-LABEL: hadds_i_const_bothhigh:
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; CHECK: // %bb.0:
316-
; CHECK-NEXT: mov w8, #32766
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; CHECK-NEXT: mov w8, #32766 // =0x7ffe
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; CHECK-NEXT: dup v0.8h, w8
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; CHECK-NEXT: ret
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%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>)
@@ -667,7 +667,244 @@ define <8 x i16> @rhadds_i_undef(<8 x i16> %t, <8 x i16> %src1) {
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ret <8 x i16> %result
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}
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670-
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i8> @shadd_v8i8(<8 x i8> %x) {
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; CHECK-LABEL: shadd_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shadd v0.8b, v0.8b, v0.8b
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; CHECK-NEXT: ret
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%r = tail call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %x, <8 x i8> %x)
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ret <8 x i8> %r
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}
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define <4 x i16> @shadd_v4i16(<4 x i16> %x) {
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; CHECK-LABEL: shadd_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shadd v0.4h, v0.4h, v0.4h
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; CHECK-NEXT: ret
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%r = tail call <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16> %x, <4 x i16> %x)
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ret <4 x i16> %r
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}
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define <2 x i32> @shadd_v2i32(<2 x i32> %x) {
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; CHECK-LABEL: shadd_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shadd v0.2s, v0.2s, v0.2s
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; CHECK-NEXT: ret
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%r = tail call <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32> %x, <2 x i32> %x)
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ret <2 x i32> %r
696+
}
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define <16 x i8> @shadd_v16i8(<16 x i8> %x) {
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; CHECK-LABEL: shadd_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shadd v0.16b, v0.16b, v0.16b
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; CHECK-NEXT: ret
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%r = tail call <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8> %x, <16 x i8> %x)
704+
ret <16 x i8> %r
705+
}
706+
707+
define <8 x i16> @shadd_v8i16(<8 x i16> %x) {
708+
; CHECK-LABEL: shadd_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shadd v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: ret
712+
%r = tail call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x, <8 x i16> %x)
713+
ret <8 x i16> %r
714+
}
715+
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define <4 x i32> @shadd_v4i32(<4 x i32> %x) {
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; CHECK-LABEL: shadd_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shadd v0.4s, v0.4s, v0.4s
720+
; CHECK-NEXT: ret
721+
%r = tail call <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32> %x, <4 x i32> %x)
722+
ret <4 x i32> %r
723+
}
724+
725+
define <8 x i8> @uhadd_v8i8(<8 x i8> %x) {
726+
; CHECK-LABEL: uhadd_v8i8:
727+
; CHECK: // %bb.0:
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; CHECK-NEXT: uhadd v0.8b, v0.8b, v0.8b
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; CHECK-NEXT: ret
730+
%r = tail call <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
731+
ret <8 x i8> %r
732+
}
733+
734+
define <4 x i16> @uhadd_v4i16(<4 x i16> %x) {
735+
; CHECK-LABEL: uhadd_v4i16:
736+
; CHECK: // %bb.0:
737+
; CHECK-NEXT: uhadd v0.4h, v0.4h, v0.4h
738+
; CHECK-NEXT: ret
739+
%r = tail call <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
740+
ret <4 x i16> %r
741+
}
742+
743+
define <2 x i32> @uhadd_v2i32(<2 x i32> %x) {
744+
; CHECK-LABEL: uhadd_v2i32:
745+
; CHECK: // %bb.0:
746+
; CHECK-NEXT: uhadd v0.2s, v0.2s, v0.2s
747+
; CHECK-NEXT: ret
748+
%r = tail call <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
749+
ret <2 x i32> %r
750+
}
751+
752+
define <16 x i8> @uhadd_v16i8(<16 x i8> %x) {
753+
; CHECK-LABEL: uhadd_v16i8:
754+
; CHECK: // %bb.0:
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; CHECK-NEXT: uhadd v0.16b, v0.16b, v0.16b
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; CHECK-NEXT: ret
757+
%r = tail call <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
758+
ret <16 x i8> %r
759+
}
760+
761+
define <8 x i16> @uhadd_v8i16(<8 x i16> %x) {
762+
; CHECK-LABEL: uhadd_v8i16:
763+
; CHECK: // %bb.0:
764+
; CHECK-NEXT: uhadd v0.8h, v0.8h, v0.8h
765+
; CHECK-NEXT: ret
766+
%r = tail call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
767+
ret <8 x i16> %r
768+
}
769+
770+
define <4 x i32> @uhadd_v4i32(<4 x i32> %x) {
771+
; CHECK-LABEL: uhadd_v4i32:
772+
; CHECK: // %bb.0:
773+
; CHECK-NEXT: uhadd v0.4s, v0.4s, v0.4s
774+
; CHECK-NEXT: ret
775+
%r = tail call <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
776+
ret <4 x i32> %r
777+
}
778+
define <8 x i8> @srhadd_v8i8(<8 x i8> %x) {
779+
; CHECK-LABEL: srhadd_v8i8:
780+
; CHECK: // %bb.0:
781+
; CHECK-NEXT: srhadd v0.8b, v0.8b, v0.8b
782+
; CHECK-NEXT: ret
783+
%r = tail call <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
784+
ret <8 x i8> %r
785+
}
786+
787+
define <4 x i16> @srhadd_v4i16(<4 x i16> %x) {
788+
; CHECK-LABEL: srhadd_v4i16:
789+
; CHECK: // %bb.0:
790+
; CHECK-NEXT: srhadd v0.4h, v0.4h, v0.4h
791+
; CHECK-NEXT: ret
792+
%r = tail call <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
793+
ret <4 x i16> %r
794+
}
795+
796+
define <2 x i32> @srhadd_v2i32(<2 x i32> %x) {
797+
; CHECK-LABEL: srhadd_v2i32:
798+
; CHECK: // %bb.0:
799+
; CHECK-NEXT: srhadd v0.2s, v0.2s, v0.2s
800+
; CHECK-NEXT: ret
801+
%r = tail call <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
802+
ret <2 x i32> %r
803+
}
804+
805+
define <16 x i8> @srhadd_v16i8(<16 x i8> %x) {
806+
; CHECK-LABEL: srhadd_v16i8:
807+
; CHECK: // %bb.0:
808+
; CHECK-NEXT: srhadd v0.16b, v0.16b, v0.16b
809+
; CHECK-NEXT: ret
810+
%r = tail call <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
811+
ret <16 x i8> %r
812+
}
813+
814+
define <8 x i16> @srhadd_v8i16(<8 x i16> %x) {
815+
; CHECK-LABEL: srhadd_v8i16:
816+
; CHECK: // %bb.0:
817+
; CHECK-NEXT: srhadd v0.8h, v0.8h, v0.8h
818+
; CHECK-NEXT: ret
819+
%r = tail call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
820+
ret <8 x i16> %r
821+
}
822+
823+
define <4 x i32> @srhadd_v4i32(<4 x i32> %x) {
824+
; CHECK-LABEL: srhadd_v4i32:
825+
; CHECK: // %bb.0:
826+
; CHECK-NEXT: srhadd v0.4s, v0.4s, v0.4s
827+
; CHECK-NEXT: ret
828+
%r = tail call <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
829+
ret <4 x i32> %r
830+
}
831+
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define <8 x i8> @urhadd_v8i8(<8 x i8> %x) {
833+
; CHECK-LABEL: urhadd_v8i8:
834+
; CHECK: // %bb.0:
835+
; CHECK-NEXT: urhadd v0.8b, v0.8b, v0.8b
836+
; CHECK-NEXT: ret
837+
%r = tail call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
838+
ret <8 x i8> %r
839+
}
840+
841+
define <4 x i16> @urhadd_v4i16(<4 x i16> %x) {
842+
; CHECK-LABEL: urhadd_v4i16:
843+
; CHECK: // %bb.0:
844+
; CHECK-NEXT: urhadd v0.4h, v0.4h, v0.4h
845+
; CHECK-NEXT: ret
846+
%r = tail call <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
847+
ret <4 x i16> %r
848+
}
849+
850+
define <2 x i32> @urhadd_v2i32(<2 x i32> %x) {
851+
; CHECK-LABEL: urhadd_v2i32:
852+
; CHECK: // %bb.0:
853+
; CHECK-NEXT: urhadd v0.2s, v0.2s, v0.2s
854+
; CHECK-NEXT: ret
855+
%r = tail call <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
856+
ret <2 x i32> %r
857+
}
858+
859+
define <16 x i8> @urhadd_v16i8(<16 x i8> %x) {
860+
; CHECK-LABEL: urhadd_v16i8:
861+
; CHECK: // %bb.0:
862+
; CHECK-NEXT: urhadd v0.16b, v0.16b, v0.16b
863+
; CHECK-NEXT: ret
864+
%r = tail call <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
865+
ret <16 x i8> %r
866+
}
867+
868+
define <8 x i16> @urhadd_v8i16(<8 x i16> %x) {
869+
; CHECK-LABEL: urhadd_v8i16:
870+
; CHECK: // %bb.0:
871+
; CHECK-NEXT: urhadd v0.8h, v0.8h, v0.8h
872+
; CHECK-NEXT: ret
873+
%r = tail call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
874+
ret <8 x i16> %r
875+
}
876+
877+
define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
878+
; CHECK-LABEL: urhadd_v4i32:
879+
; CHECK: // %bb.0:
880+
; CHECK-NEXT: urhadd v0.4s, v0.4s, v0.4s
881+
; CHECK-NEXT: ret
882+
%r = tail call <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
883+
ret <4 x i32> %r
884+
}
885+
886+
declare <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8>, <8 x i8>)
887+
declare <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16>, <4 x i16>)
888+
declare <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32>, <2 x i32>)
889+
declare <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8>, <8 x i8>)
890+
declare <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16>, <4 x i16>)
891+
declare <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32>, <2 x i32>)
892+
declare <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8>, <16 x i8>)
671893
declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)
672-
declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)
894+
declare <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32>, <4 x i32>)
895+
declare <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8>, <16 x i8>)
896+
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
897+
declare <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32>, <4 x i32>)
898+
899+
declare <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>)
900+
declare <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>)
901+
declare <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>)
902+
declare <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8>, <8 x i8>)
903+
declare <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16>, <4 x i16>)
904+
declare <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32>, <2 x i32>)
905+
declare <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8>, <16 x i8>)
673906
declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
907+
declare <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32>, <4 x i32>)
908+
declare <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8>, <16 x i8>)
909+
declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)
910+
declare <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32>, <4 x i32>)

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