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[SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is…
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… an immediate.

Differential Revision: https://reviews.llvm.org/D128479
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@paulwalker-arm
paulwalker-arm committed Jun 30, 2022
1 parent e159abd commit 2be4a7a
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Showing 4 changed files with 39 additions and 40 deletions.
28 changes: 22 additions & 6 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
View file
Expand Up @@ -4741,6 +4741,10 @@ multiclass SVE_SETCC_Pat_With_Zero<CondCode cc, CondCode invcc, ValueType predvt
(cmp $Op1, $Op2)>;
def : Pat<(predvt (AArch64setcc_z predvt:$Op1, (SVEDup0), intvt:$Op2, invcc)),
(cmp $Op1, $Op2)>;
def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z (predvt (AArch64ptrue 31)), intvt:$Op1, (SVEDup0), cc))),
(cmp $Pg, $Op1)>;
def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z (predvt (AArch64ptrue 31)), (SVEDup0), intvt:$Op1, invcc))),
(cmp $Pg, $Op1)>;
}

multiclass sve_int_cmp_0<bits<3> opc, string asm, CondCode cc, CondCode invcc> {
Expand Down Expand Up @@ -4812,14 +4816,26 @@ multiclass SVE_SETCC_Imm_Pat<CondCode cc, CondCode commuted_cc,
ValueType predvt, ValueType intvt,
Operand immtype, Instruction cmp> {
def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
(intvt ZPR:$Zs1),
(intvt (splat_vector (immtype:$imm))),
cc)),
(intvt ZPR:$Zs1),
(intvt (splat_vector (immtype:$imm))),
cc)),
(cmp $Pg, $Zs1, immtype:$imm)>;
def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
(intvt (splat_vector (immtype:$imm))),
(intvt ZPR:$Zs1),
commuted_cc)),
(intvt (splat_vector (immtype:$imm))),
(intvt ZPR:$Zs1),
commuted_cc)),
(cmp $Pg, $Zs1, immtype:$imm)>;
def : Pat<(predvt (and predvt:$Pg,
(AArch64setcc_z (predvt (AArch64ptrue 31)),
(intvt ZPR:$Zs1),
(intvt (splat_vector (immtype:$imm))),
cc))),
(cmp $Pg, $Zs1, immtype:$imm)>;
def : Pat<(predvt (and predvt:$Pg,
(AArch64setcc_z (predvt (AArch64ptrue 31)),
(intvt (splat_vector (immtype:$imm))),
(intvt ZPR:$Zs1),
commuted_cc))),
(cmp $Pg, $Zs1, immtype:$imm)>;
}

Expand Down
18 changes: 6 additions & 12 deletions llvm/test/CodeGen/AArch64/sve-fcmp.ll
View file
Expand Up @@ -435,8 +435,7 @@ define <vscale x 4 x i1> @une_zero(<vscale x 4 x float> %x) {
define <vscale x 8 x i1> @oeq_zero_pred(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
; CHECK-LABEL: oeq_zero_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.h, #0 // =0x0
; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, z1.h
; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ret
%y = fcmp oeq <vscale x 8 x half> %x, zeroinitializer
%z = and <vscale x 8 x i1> %pg, %y
Expand All @@ -445,8 +444,7 @@ define <vscale x 8 x i1> @oeq_zero_pred(<vscale x 8 x i1> %pg, <vscale x 8 x hal
define <vscale x 4 x i1> @ogt_zero_pred(<vscale x 4 x i1> %pg, <vscale x 4 x half> %x) {
; CHECK-LABEL: ogt_zero_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.h, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z1.h
; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ret
%y = fcmp ogt <vscale x 4 x half> %x, zeroinitializer
%z = and <vscale x 4 x i1> %pg, %y
Expand All @@ -455,8 +453,7 @@ define <vscale x 4 x i1> @ogt_zero_pred(<vscale x 4 x i1> %pg, <vscale x 4 x hal
define <vscale x 2 x i1> @oge_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x half> %x) {
; CHECK-LABEL: oge_zero_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.h, #0 // =0x0
; CHECK-NEXT: fcmge p0.h, p0/z, z0.h, z1.h
; CHECK-NEXT: fcmge p0.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ret
%y = fcmp oge <vscale x 2 x half> %x, zeroinitializer
%z = and <vscale x 2 x i1> %pg, %y
Expand All @@ -465,8 +462,7 @@ define <vscale x 2 x i1> @oge_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x hal
define <vscale x 4 x i1> @olt_zero_pred(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
; CHECK-LABEL: olt_zero_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.s, #0 // =0x0
; CHECK-NEXT: fcmgt p0.s, p0/z, z1.s, z0.s
; CHECK-NEXT: fcmlt p0.s, p0/z, z0.s, #0.0
; CHECK-NEXT: ret
%y = fcmp olt <vscale x 4 x float> %x, zeroinitializer
%z = and <vscale x 4 x i1> %pg, %y
Expand All @@ -475,8 +471,7 @@ define <vscale x 4 x i1> @olt_zero_pred(<vscale x 4 x i1> %pg, <vscale x 4 x flo
define <vscale x 2 x i1> @ole_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x float> %x) {
; CHECK-LABEL: ole_zero_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.s, #0 // =0x0
; CHECK-NEXT: fcmge p0.s, p0/z, z1.s, z0.s
; CHECK-NEXT: fcmle p0.s, p0/z, z0.s, #0.0
; CHECK-NEXT: ret
%y = fcmp ole <vscale x 2 x float> %x, zeroinitializer
%z = and <vscale x 2 x i1> %pg, %y
Expand All @@ -485,8 +480,7 @@ define <vscale x 2 x i1> @ole_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x flo
define <vscale x 2 x i1> @une_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
; CHECK-LABEL: une_zero_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.d, #0 // =0x0
; CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d
; CHECK-NEXT: fcmne p0.d, p0/z, z0.d, #0.0
; CHECK-NEXT: ret
%y = fcmp une <vscale x 2 x double> %x, zeroinitializer
%z = and <vscale x 2 x i1> %pg, %y
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll
View file
Expand Up @@ -112,8 +112,7 @@ define i1 @ptest_and_v16i1_512bit_sve(float* %a, float * %b) vscale_range(4, 4)
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0
; CHECK-NEXT: mov z0.s, #0 // =0x0
; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, z0.s
; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.0
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: ptrue p0.b, vl16
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
Expand Down
30 changes: 10 additions & 20 deletions llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
View file
Expand Up @@ -1099,8 +1099,7 @@ define <vscale x 4 x i1> @predicated_icmp_unknown_rhs(<vscale x 4 x i1> %a, <vsc
define <vscale x 16 x i1> @predicated_icmp_eq_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: predicated_icmp_eq_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.b, #0 // =0x0
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #0
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 0, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%icmp = icmp eq <vscale x 16 x i8> %b, %imm
Expand All @@ -1111,8 +1110,7 @@ define <vscale x 16 x i1> @predicated_icmp_eq_imm(<vscale x 16 x i1> %a, <vscale
define <vscale x 8 x i1> @predicated_icmp_ne_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: predicated_icmp_ne_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.h, #-16 // =0xfffffffffffffff0
; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h
; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #-16
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -16, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%icmp = icmp ne <vscale x 8 x i16> %b, %imm
Expand All @@ -1123,8 +1121,7 @@ define <vscale x 8 x i1> @predicated_icmp_ne_imm(<vscale x 8 x i1> %a, <vscale x
define <vscale x 4 x i1> @predicated_icmp_sge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: predicated_icmp_sge_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.s, #1 // =0x1
; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s
; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #1
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%icmp = icmp sge <vscale x 4 x i32> %b, %imm
Expand All @@ -1135,8 +1132,7 @@ define <vscale x 4 x i1> @predicated_icmp_sge_imm(<vscale x 4 x i1> %a, <vscale
define <vscale x 2 x i1> @predicated_icmp_sgt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: predicated_icmp_sgt_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.d, #2 // =0x2
; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, z1.d
; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #2
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%icmp = icmp sgt <vscale x 2 x i64> %b, %imm
Expand All @@ -1147,8 +1143,7 @@ define <vscale x 2 x i1> @predicated_icmp_sgt_imm(<vscale x 2 x i1> %a, <vscale
define <vscale x 16 x i1> @predicated_icmp_sle_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: predicated_icmp_sle_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.b, #-1 // =0xffffffffffffffff
; CHECK-NEXT: cmpge p0.b, p0/z, z1.b, z0.b
; CHECK-NEXT: cmple p0.b, p0/z, z0.b, #-1
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -1, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%icmp = icmp sle <vscale x 16 x i8> %b, %imm
Expand All @@ -1159,8 +1154,7 @@ define <vscale x 16 x i1> @predicated_icmp_sle_imm(<vscale x 16 x i1> %a, <vscal
define <vscale x 8 x i1> @predicated_icmp_slt_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: predicated_icmp_slt_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.h, #-2 // =0xfffffffffffffffe
; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h
; CHECK-NEXT: cmplt p0.h, p0/z, z0.h, #-2
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -2, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%icmp = icmp slt <vscale x 8 x i16> %b, %imm
Expand All @@ -1171,8 +1165,7 @@ define <vscale x 8 x i1> @predicated_icmp_slt_imm(<vscale x 8 x i1> %a, <vscale
define <vscale x 4 x i1> @predicated_icmp_uge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: predicated_icmp_uge_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.s, #1 // =0x1
; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z1.s
; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #1
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%icmp = icmp uge <vscale x 4 x i32> %b, %imm
Expand All @@ -1183,8 +1176,7 @@ define <vscale x 4 x i1> @predicated_icmp_uge_imm(<vscale x 4 x i1> %a, <vscale
define <vscale x 2 x i1> @predicated_icmp_ugt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: predicated_icmp_ugt_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.d, #2 // =0x2
; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, z1.d
; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #2
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%icmp = icmp ugt <vscale x 2 x i64> %b, %imm
Expand All @@ -1195,8 +1187,7 @@ define <vscale x 2 x i1> @predicated_icmp_ugt_imm(<vscale x 2 x i1> %a, <vscale
define <vscale x 16 x i1> @predicated_icmp_ule_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: predicated_icmp_ule_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.b, #3 // =0x3
; CHECK-NEXT: cmphs p0.b, p0/z, z1.b, z0.b
; CHECK-NEXT: cmpls p0.b, p0/z, z0.b, #3
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%icmp = icmp ule <vscale x 16 x i8> %b, %imm
Expand All @@ -1207,8 +1198,7 @@ define <vscale x 16 x i1> @predicated_icmp_ule_imm(<vscale x 16 x i1> %a, <vscal
define <vscale x 8 x i1> @predicated_icmp_ult_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: predicated_icmp_ult_imm:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.h, #127 // =0x7f
; CHECK-NEXT: cmphi p0.h, p0/z, z1.h, z0.h
; CHECK-NEXT: cmplo p0.h, p0/z, z0.h, #127
; CHECK-NEXT: ret
%imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 127, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%icmp = icmp ult <vscale x 8 x i16> %b, %imm
Expand Down

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