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[SCEV] Generalize implication when signedness of FoundPred doesn't ma…
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…tter

The implication logic for two values that are both negative or non-negative
says that it doesn't matter whether their predicate is signed and unsigned,
but only flips unsigned into signed for further inference. This patch adds
support for flipping a signed predicate into unsigned as well.

Differential Revision: https://reviews.llvm.org/D109959
Reviewed By: nikic
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xortator committed Sep 21, 2021
1 parent ea72b03 commit 2c7d5fb
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Showing 2 changed files with 8 additions and 5 deletions.
9 changes: 7 additions & 2 deletions llvm/lib/Analysis/ScalarEvolution.cpp
Expand Up @@ -10704,8 +10704,13 @@ bool ScalarEvolution::isImpliedCondBalancedTypes(

// Unsigned comparison is the same as signed comparison when both the operands
// are non-negative or negative.
if (CmpInst::isUnsigned(FoundPred) &&
CmpInst::getSignedPredicate(FoundPred) == Pred &&
auto IsSignFlippedPredicate = [](CmpInst::Predicate P1,
CmpInst::Predicate P2) {
assert(P1 != P2 && "Handled earlier!");
return CmpInst::isRelational(P2) &&
P1 == CmpInst::getFlippedSignednessPredicate(P2);
};
if (IsSignFlippedPredicate(Pred, FoundPred) &&
((isKnownNonNegative(FoundLHS) && isKnownNonNegative(FoundRHS)) ||
(isKnownNegative(FoundLHS) && isKnownNegative(FoundRHS))))
return isImpliedCondOperands(Pred, LHS, RHS, FoundLHS, FoundRHS, CtxI);
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4 changes: 1 addition & 3 deletions llvm/test/Transforms/IndVarSimplify/negative_ranges.ll
Expand Up @@ -4,7 +4,6 @@

declare i1 @cond()

; FIXME: 2nd check is implied by the 1st one as both values are negative.
define i32 @test_01(i32* %p, i32* %s) {
; CHECK-LABEL: @test_01(
; CHECK-NEXT: entry:
Expand All @@ -16,8 +15,7 @@ define i32 @test_01(i32* %p, i32* %s) {
; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[IV]], [[END]]
; CHECK-NEXT: br i1 [[C1]], label [[GUARDED:%.*]], label [[SIDE_EXIT:%.*]]
; CHECK: guarded:
; CHECK-NEXT: [[C2:%.*]] = icmp ult i32 [[IV]], [[END]]
; CHECK-NEXT: br i1 [[C2]], label [[BACKEDGE]], label [[SIDE_EXIT]]
; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[SIDE_EXIT]]
; CHECK: backedge:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[LOOP_COND:%.*]] = call i1 @cond()
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