[X86] Handle COPYs of physregs better (regalloc hints)

Enable enableMultipleCopyHints() on X86.

Original Patch by @jonpa:

While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling.

Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates.

Differential Revision: https://reviews.llvm.org/D38128

llvm-svn: 342578

llvm/lib/Target/X86/X86RegisterInfo.h

@@ -95,6 +95,8 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                                MachineFunction &MF) const override;
 
+  bool enableMultipleCopyHints() const override { return true; }
+
   /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee-save registers on this target.
   const MCPhysReg *

llvm/test/CodeGen/X86/GlobalISel/add-scalar.ll

@@ -54,14 +54,15 @@ define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
   ret i16 %ret
 }
 
-define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
-; X64-LABEL: test_add_i8:
-; X64:       # %bb.0:
-; X64-NEXT:    addb %dil, %sil
-; X64-NEXT:    movl %esi, %eax
-; X64-NEXT:    retq
-;
-; X32-LABEL: test_add_i8:
+define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
+; X64-LABEL: test_add_i8:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %esi, %eax
+; X64-NEXT:    addb %dil, %al
+; X64-NEXT:    # kill: def $al killed $al killed $eax
+; X64-NEXT:    retq
+;
+; X32-LABEL: test_add_i8:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    addb {{[0-9]+}}(%esp), %al

llvm/test/CodeGen/X86/GlobalISel/and-scalar.ll

@@ -16,43 +16,45 @@ define i32 @test_and_i1(i32 %arg1, i32 %arg2) {
   ret i32 %ret
 }
 
-define i8 @test_and_i8(i8 %arg1, i8 %arg2) {
-; ALL-LABEL: test_and_i8:
-; ALL:       # %bb.0:
-; ALL-NEXT:    andb %dil, %sil
-; ALL-NEXT:    movl %esi, %eax
-; ALL-NEXT:    retq
-  %ret = and i8 %arg1, %arg2
-  ret i8 %ret
-}
-
-define i16 @test_and_i16(i16 %arg1, i16 %arg2) {
-; ALL-LABEL: test_and_i16:
-; ALL:       # %bb.0:
-; ALL-NEXT:    andw %di, %si
-; ALL-NEXT:    movl %esi, %eax
-; ALL-NEXT:    retq
-  %ret = and i16 %arg1, %arg2
-  ret i16 %ret
-}
-
-define i32 @test_and_i32(i32 %arg1, i32 %arg2) {
-; ALL-LABEL: test_and_i32:
-; ALL:       # %bb.0:
-; ALL-NEXT:    andl %edi, %esi
-; ALL-NEXT:    movl %esi, %eax
-; ALL-NEXT:    retq
-  %ret = and i32 %arg1, %arg2
-  ret i32 %ret
-}
-
-define i64 @test_and_i64(i64 %arg1, i64 %arg2) {
-; ALL-LABEL: test_and_i64:
-; ALL:       # %bb.0:
-; ALL-NEXT:    andq %rdi, %rsi
-; ALL-NEXT:    movq %rsi, %rax
-; ALL-NEXT:    retq
-  %ret = and i64 %arg1, %arg2
-  ret i64 %ret
+define i8 @test_and_i8(i8 %arg1, i8 %arg2) {
+; ALL-LABEL: test_and_i8:
+; ALL:       # %bb.0:
+; ALL-NEXT:    movl %esi, %eax
+; ALL-NEXT:    andb %dil, %al
+; ALL-NEXT:    # kill: def $al killed $al killed $eax
+; ALL-NEXT:    retq
+  %ret = and i8 %arg1, %arg2
+  ret i8 %ret
+}
+
+define i16 @test_and_i16(i16 %arg1, i16 %arg2) {
+; ALL-LABEL: test_and_i16:
+; ALL:       # %bb.0:
+; ALL-NEXT:    movl %esi, %eax
+; ALL-NEXT:    andw %di, %ax
+; ALL-NEXT:    # kill: def $ax killed $ax killed $eax
+; ALL-NEXT:    retq
+  %ret = and i16 %arg1, %arg2
+  ret i16 %ret
+}
+
+define i32 @test_and_i32(i32 %arg1, i32 %arg2) {
+; ALL-LABEL: test_and_i32:
+; ALL:       # %bb.0:
+; ALL-NEXT:    movl %esi, %eax
+; ALL-NEXT:    andl %edi, %eax
+; ALL-NEXT:    retq
+  %ret = and i32 %arg1, %arg2
+  ret i32 %ret
+}
+
+define i64 @test_and_i64(i64 %arg1, i64 %arg2) {
+; ALL-LABEL: test_and_i64:
+; ALL:       # %bb.0:
+; ALL-NEXT:    movq %rsi, %rax
+; ALL-NEXT:    andq %rdi, %rax
+; ALL-NEXT:    retq
+  %ret = and i64 %arg1, %arg2
+  ret i64 %ret
 }