[ASan][AMDGPU] Make shadow offset match X86 on Linux

This patch explicitly sets the shadow offset for AMDGPU to match that of X86 on Linux. Reviewed By: vitalybuka https://reviews.llvm.org/D105282
llvm · Jul 9, 2021 · 2e194de · 2e194de
1 parent ed102ce
commit 2e194de
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Showing 4 changed files with 8 additions and 9 deletions.
diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -465,10 +465,6 @@ static ShadowMapping getShadowMapping(Triple &TargetTriple, int LongSize,
   bool IsEmscripten = TargetTriple.isOSEmscripten();
   bool IsAMDGPU = TargetTriple.isAMDGPU();
 
-  // Asan support for AMDGPU assumes X86 as the host right now.
-  if (IsAMDGPU)
-    IsX86_64 = true;
-
   ShadowMapping Mapping;
 
   Mapping.Scale = kDefaultShadowScale;
@@ -532,6 +528,9 @@ static ShadowMapping getShadowMapping(Triple &TargetTriple, int LongSize,
       Mapping.Offset = kAArch64_ShadowOffset64;
     else if (IsRISCV64)
       Mapping.Offset = kRISCV64_ShadowOffset64;
+    else if (IsAMDGPU)
+      Mapping.Offset = (kSmallX86_64ShadowOffsetBase &
+                        (kSmallX86_64ShadowOffsetAlignMask << Mapping.Scale));
     else
       Mapping.Offset = kDefaultShadowOffset64;
   }

diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
@@ -12,7 +12,7 @@ entry:
 ;
 ; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(4)* %a to i64
 ; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
 ; CHECK:   icmp ne i8

diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
@@ -16,7 +16,7 @@ entry:
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
@@ -53,7 +53,7 @@ entry:
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8

diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
@@ -10,7 +10,7 @@ entry:
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   or
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
@@ -40,7 +40,7 @@ entry:
 ;
 ; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64
 ; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   {{add|or}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
 ; CHECK:   icmp ne i8