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[ARM] Ignore Implicit CPSR regs when lowering from Machine to MC oper…
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…ands

The code here seems to date back to r134705, when tablegen lowering was first
being added. I don't believe that we need to include CPSR implicit operands on
the MCInst. This now works more like other backends (like AArch64), where all
implicit registers are skipped.

This allows the AliasInst for CSEL's to match correctly, as can be seen in the
test changes.

Differential revision: https://reviews.llvm.org/D66703

llvm-svn: 370745
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@davemgreen
davemgreen committed Sep 3, 2019
1 parent 92b2be1 commit 2f3574c
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Showing 20 changed files with 682 additions and 670 deletions.
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMMCInstLower.cpp
View file
Expand Up @@ -74,8 +74,8 @@ bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
switch (MO.getType()) {
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all non-CPSR implicit register operands.
if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
// Ignore all implicit register operands.
if (MO.isImplicit())
return false;
assert(!MO.getSubReg() && "Subregs should be eliminated!");
MCOp = MCOperand::createReg(MO.getReg());
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/Thumb2/csel.ll
View file
Expand Up @@ -6,7 +6,7 @@ define i32 @csinc_const_65(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinc r0, r1, r1, le
; CHECK-NEXT: cinc r0, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand All @@ -19,7 +19,7 @@ define i32 @csinc_const_56(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinc r0, r1, r1, gt
; CHECK-NEXT: cinc r0, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand All @@ -31,7 +31,7 @@ define i32 @csinc_const_zext(i32 %a) {
; CHECK-LABEL: csinc_const_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinc r0, zr, zr, le
; CHECK-NEXT: cset r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand All @@ -44,7 +44,7 @@ define i32 @csinv_const_56(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinv r0, r1, r1, le
; CHECK-NEXT: cinv r0, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand All @@ -57,7 +57,7 @@ define i32 @csinv_const_65(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinv r0, r1, r1, gt
; CHECK-NEXT: cinv r0, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand All @@ -69,7 +69,7 @@ define i32 @csinv_const_sext(i32 %a) {
; CHECK-LABEL: csinv_const_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinv r0, zr, zr, le
; CHECK-NEXT: csetm r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand All @@ -82,7 +82,7 @@ define i32 @csneg_const(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csneg r0, r1, r1, gt
; CHECK-NEXT: cneg r0, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand All @@ -95,7 +95,7 @@ define i32 @csneg_const_r(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csneg r0, r1, r1, le
; CHECK-NEXT: cneg r0, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
Expand Down Expand Up @@ -316,7 +316,7 @@ define i32 @csinc_inplace(i32 %a, i32 %b) {
; CHECK-LABEL: csinc_inplace:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45
; CHECK-NEXT: csinc r0, r0, r0, le
; CHECK-NEXT: cinc r0, r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %b, 45
Expand All @@ -329,7 +329,7 @@ define i32 @csinv_inplace(i32 %a, i32 %b) {
; CHECK-LABEL: csinv_inplace:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45
; CHECK-NEXT: csinv r0, r0, r0, le
; CHECK-NEXT: cinv r0, r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %b, 45
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Thumb2/mve-abs.ll
View file
Expand Up @@ -49,7 +49,7 @@ define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) {
; CHECK-NEXT: rsbs.w r3, lr, #0
; CHECK-NEXT: sbc.w r2, r12, r0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r1, zr, zr, pl
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r2, r0
Expand All @@ -61,7 +61,7 @@ define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) {
; CHECK-NEXT: rsbs.w r2, lr, #0
; CHECK-NEXT: sbc.w r3, r12, r0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r1, zr, zr, pl
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq r2, lr
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Thumb2/mve-fmath.ll
View file
Expand Up @@ -1329,14 +1329,14 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: ldrb.w r1, [sp, #25]
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vabs.f16 s8, s1
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: tst.w r1, #128
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: csinc r1, zr, zr, eq
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: lsls r1, r1, #31
Expand All @@ -1348,7 +1348,7 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
Expand All @@ -1358,7 +1358,7 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
Expand All @@ -1367,7 +1367,7 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: ldrb.w r0, [sp, #13]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
Expand All @@ -1378,7 +1378,7 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
Expand All @@ -1387,14 +1387,14 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: ldrb.w r0, [sp, #5]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/Thumb2/mve-minmax.ll
View file
Expand Up @@ -55,13 +55,13 @@ define arm_aapcs_vfpcc <2 x i64> @smin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
Expand Down Expand Up @@ -129,13 +129,13 @@ define arm_aapcs_vfpcc <2 x i64> @umin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
Expand Down Expand Up @@ -204,13 +204,13 @@ define arm_aapcs_vfpcc <2 x i64> @smax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
Expand Down Expand Up @@ -278,13 +278,13 @@ define arm_aapcs_vfpcc <2 x i64> @umax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
Expand Down Expand Up @@ -386,14 +386,14 @@ define arm_aapcs_vfpcc <2 x double> @maxnm_float64_t(<2 x double> %src1, <2 x do
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r4, zr, zr, eq
; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.32 q0[2], r4
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/Thumb2/mve-pred-and.ll
View file
Expand Up @@ -612,16 +612,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q1, q1, q3
Expand All @@ -648,9 +648,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
Expand All @@ -659,24 +659,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vand q2, q2, q3
Expand All @@ -700,9 +700,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: csinc r2, zr, zr, ne
; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csinv r2, zr, zr, eq
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov r2, s7
Expand All @@ -711,24 +711,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vand q2, q3, q2
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
View file
Expand Up @@ -155,9 +155,9 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: csinc r1, zr, zr, ne
; CHECK-NEXT: cset r1, eq
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r1, #1
Expand Down

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