Skip to content

Commit

Permalink
WebAssembly: textual emission uses expected opcode names
Browse files Browse the repository at this point in the history 
Summary: WebAssembly's tablegen instructions have the names WebAssembly expects, but by LLVM convention they're uppercase and suffixed with their type after an underscore. Leave the C++ code that way, but print outt he names WebAssembly expects (lowercase, no type). We could teach tablegen to do this later, maybe by using `!cast<string>(node)` in the .td files.

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D11776

llvm-svn: 244305
  • Loading branch information
@jfbastien
jfbastien committed Aug 7, 2015
1 parent f594fca commit 315cc06
Show file tree
Hide file tree
Showing 3 changed files with 45 additions and 44 deletions.
25 changes: 13 additions & 12 deletions llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
View file
Expand Up @@ -74,6 +74,17 @@ class WebAssemblyAsmPrinter final : public AsmPrinter {

//===----------------------------------------------------------------------===//

// Untyped, lower-case version of the opcode's name matching the names
// WebAssembly opcodes are expected to have. The tablegen names are uppercase
// and suffixed with their type (after an underscore).
static SmallString<32> Name(const WebAssemblyInstrInfo *TII,
const MachineInstr *MI) {
std::string N(StringRef(TII->getName(MI->getOpcode())).lower());
std::string::size_type End = N.find('_');
End = std::string::npos == End ? N.length() : End;
return SmallString<32>(&N[0], &N[End]);
}

void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
SmallString<128> Str;
raw_svector_ostream OS(Str);
Expand All @@ -96,21 +107,11 @@ void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
case WebAssembly::ARGUMENT_Int64:
case WebAssembly::ARGUMENT_Float32:
case WebAssembly::ARGUMENT_Float64:
OS << "argument " << MI->getOperand(1).getImm();
OS << Name(TII, MI) << ' ' << MI->getOperand(1).getImm();
PrintOperands = false;
break;
case WebAssembly::RETURN_Int32:
case WebAssembly::RETURN_Int64:
case WebAssembly::RETURN_Float32:
case WebAssembly::RETURN_Float64:
case WebAssembly::RETURN_VOID:
// FIXME This is here only so "return" prints nicely, instead of printing
// the isel name. Other operations have the same problem, fix this in
// a generic way instead.
OS << "return";
break;
default:
OS << TII->getName(MI->getOpcode());
OS << Name(TII, MI);
break;
}

Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/WebAssembly/integer32.ll
View file
Expand Up @@ -12,7 +12,7 @@ declare i32 @llvm.ctpop.i32(i32)
; CHECK-LABEL: add32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (ADD_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (add @1 @0))
; CHECK-NEXT: (return @2)
define i32 @add32(i32 %x, i32 %y) {
%a = add i32 %x, %y
Expand All @@ -22,7 +22,7 @@ define i32 @add32(i32 %x, i32 %y) {
; CHECK-LABEL: sub32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SUB_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (sub @1 @0))
; CHECK-NEXT: (return @2)
define i32 @sub32(i32 %x, i32 %y) {
%a = sub i32 %x, %y
Expand All @@ -32,7 +32,7 @@ define i32 @sub32(i32 %x, i32 %y) {
; CHECK-LABEL: mul32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (MUL_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (mul @1 @0))
; CHECK-NEXT: (return @2)
define i32 @mul32(i32 %x, i32 %y) {
%a = mul i32 %x, %y
Expand All @@ -42,7 +42,7 @@ define i32 @mul32(i32 %x, i32 %y) {
; CHECK-LABEL: sdiv32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SDIV_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (sdiv @1 @0))
; CHECK-NEXT: (return @2)
define i32 @sdiv32(i32 %x, i32 %y) {
%a = sdiv i32 %x, %y
Expand All @@ -52,7 +52,7 @@ define i32 @sdiv32(i32 %x, i32 %y) {
; CHECK-LABEL: udiv32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (UDIV_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (udiv @1 @0))
; CHECK-NEXT: (return @2)
define i32 @udiv32(i32 %x, i32 %y) {
%a = udiv i32 %x, %y
Expand All @@ -62,7 +62,7 @@ define i32 @udiv32(i32 %x, i32 %y) {
; CHECK-LABEL: srem32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SREM_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (srem @1 @0))
; CHECK-NEXT: (return @2)
define i32 @srem32(i32 %x, i32 %y) {
%a = srem i32 %x, %y
Expand All @@ -72,7 +72,7 @@ define i32 @srem32(i32 %x, i32 %y) {
; CHECK-LABEL: urem32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (UREM_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (urem @1 @0))
; CHECK-NEXT: (return @2)
define i32 @urem32(i32 %x, i32 %y) {
%a = urem i32 %x, %y
Expand All @@ -82,7 +82,7 @@ define i32 @urem32(i32 %x, i32 %y) {
; CHECK-LABEL: and32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (AND_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (and @1 @0))
; CHECK-NEXT: (return @2)
define i32 @and32(i32 %x, i32 %y) {
%a = and i32 %x, %y
Expand All @@ -92,7 +92,7 @@ define i32 @and32(i32 %x, i32 %y) {
; CHECK-LABEL: ior32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (IOR_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (ior @1 @0))
; CHECK-NEXT: (return @2)
define i32 @ior32(i32 %x, i32 %y) {
%a = or i32 %x, %y
Expand All @@ -102,7 +102,7 @@ define i32 @ior32(i32 %x, i32 %y) {
; CHECK-LABEL: xor32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (XOR_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (xor @1 @0))
; CHECK-NEXT: (return @2)
define i32 @xor32(i32 %x, i32 %y) {
%a = xor i32 %x, %y
Expand All @@ -112,7 +112,7 @@ define i32 @xor32(i32 %x, i32 %y) {
; CHECK-LABEL: shl32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SHL_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (shl @1 @0))
; CHECK-NEXT: (return @2)
define i32 @shl32(i32 %x, i32 %y) {
%a = shl i32 %x, %y
Expand All @@ -122,7 +122,7 @@ define i32 @shl32(i32 %x, i32 %y) {
; CHECK-LABEL: shr32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SHR_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (shr @1 @0))
; CHECK-NEXT: (return @2)
define i32 @shr32(i32 %x, i32 %y) {
%a = lshr i32 %x, %y
Expand All @@ -132,7 +132,7 @@ define i32 @shr32(i32 %x, i32 %y) {
; CHECK-LABEL: sar32:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SAR_I32 @1 @0))
; CHECK-NEXT: (setlocal @2 (sar @1 @0))
; CHECK-NEXT: (return @2)
define i32 @sar32(i32 %x, i32 %y) {
%a = ashr i32 %x, %y
Expand All @@ -141,7 +141,7 @@ define i32 @sar32(i32 %x, i32 %y) {

; CHECK-LABEL: clz32:
; CHECK-NEXT: (setlocal @0 (argument 0))
; CHECK-NEXT: (setlocal @1 (CLZ_I32 @0))
; CHECK-NEXT: (setlocal @1 (clz @0))
; CHECK-NEXT: (return @1)
define i32 @clz32(i32 %x) {
%a = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
Expand All @@ -150,7 +150,7 @@ define i32 @clz32(i32 %x) {

; CHECK-LABEL: ctz32:
; CHECK-NEXT: (setlocal @0 (argument 0))
; CHECK-NEXT: (setlocal @1 (CTZ_I32 @0))
; CHECK-NEXT: (setlocal @1 (ctz @0))
; CHECK-NEXT: (return @1)
define i32 @ctz32(i32 %x) {
%a = call i32 @llvm.cttz.i32(i32 %x, i1 false)
Expand All @@ -159,7 +159,7 @@ define i32 @ctz32(i32 %x) {

; CHECK-LABEL: popcnt32:
; CHECK-NEXT: (setlocal @0 (argument 0))
; CHECK-NEXT: (setlocal @1 (POPCNT_I32 @0))
; CHECK-NEXT: (setlocal @1 (popcnt @0))
; CHECK-NEXT: (return @1)
define i32 @popcnt32(i32 %x) {
%a = call i32 @llvm.ctpop.i32(i32 %x)
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/WebAssembly/integer64.ll
View file
Expand Up @@ -12,7 +12,7 @@ declare i64 @llvm.ctpop.i64(i64)
; CHECK-LABEL: add64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (ADD_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (add @1 @0))
; CHECK-NEXT: (return @2)
define i64 @add64(i64 %x, i64 %y) {
%a = add i64 %x, %y
Expand All @@ -22,7 +22,7 @@ define i64 @add64(i64 %x, i64 %y) {
; CHECK-LABEL: sub64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SUB_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (sub @1 @0))
; CHECK-NEXT: (return @2)
define i64 @sub64(i64 %x, i64 %y) {
%a = sub i64 %x, %y
Expand All @@ -32,7 +32,7 @@ define i64 @sub64(i64 %x, i64 %y) {
; CHECK-LABEL: mul64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (MUL_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (mul @1 @0))
; CHECK-NEXT: (return @2)
define i64 @mul64(i64 %x, i64 %y) {
%a = mul i64 %x, %y
Expand All @@ -42,7 +42,7 @@ define i64 @mul64(i64 %x, i64 %y) {
; CHECK-LABEL: sdiv64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SDIV_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (sdiv @1 @0))
; CHECK-NEXT: (return @2)
define i64 @sdiv64(i64 %x, i64 %y) {
%a = sdiv i64 %x, %y
Expand All @@ -52,7 +52,7 @@ define i64 @sdiv64(i64 %x, i64 %y) {
; CHECK-LABEL: udiv64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (UDIV_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (udiv @1 @0))
; CHECK-NEXT: (return @2)
define i64 @udiv64(i64 %x, i64 %y) {
%a = udiv i64 %x, %y
Expand All @@ -62,7 +62,7 @@ define i64 @udiv64(i64 %x, i64 %y) {
; CHECK-LABEL: srem64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SREM_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (srem @1 @0))
; CHECK-NEXT: (return @2)
define i64 @srem64(i64 %x, i64 %y) {
%a = srem i64 %x, %y
Expand All @@ -72,7 +72,7 @@ define i64 @srem64(i64 %x, i64 %y) {
; CHECK-LABEL: urem64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (UREM_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (urem @1 @0))
; CHECK-NEXT: (return @2)
define i64 @urem64(i64 %x, i64 %y) {
%a = urem i64 %x, %y
Expand All @@ -82,7 +82,7 @@ define i64 @urem64(i64 %x, i64 %y) {
; CHECK-LABEL: and64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (AND_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (and @1 @0))
; CHECK-NEXT: (return @2)
define i64 @and64(i64 %x, i64 %y) {
%a = and i64 %x, %y
Expand All @@ -92,7 +92,7 @@ define i64 @and64(i64 %x, i64 %y) {
; CHECK-LABEL: ior64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (IOR_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (ior @1 @0))
; CHECK-NEXT: (return @2)
define i64 @ior64(i64 %x, i64 %y) {
%a = or i64 %x, %y
Expand All @@ -102,7 +102,7 @@ define i64 @ior64(i64 %x, i64 %y) {
; CHECK-LABEL: xor64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (XOR_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (xor @1 @0))
; CHECK-NEXT: (return @2)
define i64 @xor64(i64 %x, i64 %y) {
%a = xor i64 %x, %y
Expand All @@ -112,7 +112,7 @@ define i64 @xor64(i64 %x, i64 %y) {
; CHECK-LABEL: shl64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SHL_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (shl @1 @0))
; CHECK-NEXT: (return @2)
define i64 @shl64(i64 %x, i64 %y) {
%a = shl i64 %x, %y
Expand All @@ -122,7 +122,7 @@ define i64 @shl64(i64 %x, i64 %y) {
; CHECK-LABEL: shr64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SHR_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (shr @1 @0))
; CHECK-NEXT: (return @2)
define i64 @shr64(i64 %x, i64 %y) {
%a = lshr i64 %x, %y
Expand All @@ -132,7 +132,7 @@ define i64 @shr64(i64 %x, i64 %y) {
; CHECK-LABEL: sar64:
; CHECK-NEXT: (setlocal @0 (argument 1))
; CHECK-NEXT: (setlocal @1 (argument 0))
; CHECK-NEXT: (setlocal @2 (SAR_I64 @1 @0))
; CHECK-NEXT: (setlocal @2 (sar @1 @0))
; CHECK-NEXT: (return @2)
define i64 @sar64(i64 %x, i64 %y) {
%a = ashr i64 %x, %y
Expand All @@ -141,7 +141,7 @@ define i64 @sar64(i64 %x, i64 %y) {

; CHECK-LABEL: clz64:
; CHECK-NEXT: (setlocal @0 (argument 0))
; CHECK-NEXT: (setlocal @1 (CLZ_I64 @0))
; CHECK-NEXT: (setlocal @1 (clz @0))
; CHECK-NEXT: (return @1)
define i64 @clz64(i64 %x) {
%a = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
Expand All @@ -150,7 +150,7 @@ define i64 @clz64(i64 %x) {

; CHECK-LABEL: ctz64:
; CHECK-NEXT: (setlocal @0 (argument 0))
; CHECK-NEXT: (setlocal @1 (CTZ_I64 @0))
; CHECK-NEXT: (setlocal @1 (ctz @0))
; CHECK-NEXT: (return @1)
define i64 @ctz64(i64 %x) {
%a = call i64 @llvm.cttz.i64(i64 %x, i1 false)
Expand All @@ -159,7 +159,7 @@ define i64 @ctz64(i64 %x) {

; CHECK-LABEL: popcnt64:
; CHECK-NEXT: (setlocal @0 (argument 0))
; CHECK-NEXT: (setlocal @1 (POPCNT_I64 @0))
; CHECK-NEXT: (setlocal @1 (popcnt @0))
; CHECK-NEXT: (return @1)
define i64 @popcnt64(i64 %x) {
%a = call i64 @llvm.ctpop.i64(i64 %x)
Expand Down

0 comments on commit 315cc06

Please sign in to comment.