Skip to content

Commit

Permalink
[clang][CodeGen] Regenerate tests checks after 94795a3
Browse files Browse the repository at this point in the history 
These were missed as I didn't expect clang codegen to be updated
  • Loading branch information
@RKSimon
RKSimon committed Oct 6, 2023
1 parent ef8c26b commit 32a9c09
Show file tree
Hide file tree
Showing 2 changed files with 22 additions and 24 deletions.
22 changes: 14 additions & 8 deletions clang/test/CodeGen/X86/avx-shuffle-builtins.c
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=x86_64-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=i386-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=x86_64-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X64
// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=i386-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86
// FIXME: This is testing optimized generation of shuffle instructions and should be fixed.


Expand Down Expand Up @@ -129,8 +129,11 @@ __m256i test_mm256_insertf128_si256_1(__m256i a, __m128i b) {
// Make sure we have the correct mask for each extractf128 case.

__m128 test_mm256_extractf128_ps_0(__m256 a) {
// CHECK-LABEL: test_mm256_extractf128_ps_0
// CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
// X64-LABEL: test_mm256_extractf128_ps_0
// X64: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
//
// X86-LABEL: test_mm256_extractf128_ps_0
// X86: shufflevector{{.*}}<i32 0, i32 1>
return _mm256_extractf128_ps(a, 0);
}

Expand All @@ -142,13 +145,16 @@ __m128d test_mm256_extractf128_pd_0(__m256d a) {

__m128i test_mm256_extractf128_si256_0(__m256i a) {
// CHECK-LABEL: test_mm256_extractf128_si256_0
// CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
// CHECK: shufflevector{{.*}}<i32 0, i32 1>
return _mm256_extractf128_si256(a, 0);
}

__m128 test_mm256_extractf128_ps_1(__m256 a) {
// CHECK-LABEL: test_mm256_extractf128_ps_1
// CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
// X64-LABEL: test_mm256_extractf128_ps_1
// X64: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
//
// X86-LABEL: test_mm256_extractf128_ps_1
// X86: shufflevector{{.*}}<i32 2, i32 3>
return _mm256_extractf128_ps(a, 1);
}

Expand All @@ -160,7 +166,7 @@ __m128d test_mm256_extractf128_pd_1(__m256d a) {

__m128i test_mm256_extractf128_si256_1(__m256i a) {
// CHECK-LABEL: test_mm256_extractf128_si256_1
// CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
// CHECK: shufflevector{{.*}}<i32 2, i32 3>
return _mm256_extractf128_si256(a, 1);
}

Expand Down
24 changes: 8 additions & 16 deletions clang/test/CodeGen/aarch64-neon-vcmla.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -167,10 +167,8 @@ float16x4_t test_vcmla_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t r
}

// CHECK-LABEL: @test_vcmlaq_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
// CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_lane_f16(acc, lhs, rhs, 1);
Expand Down Expand Up @@ -243,10 +241,8 @@ float16x4_t test_vcmla_rot90_laneq_f16(float16x4_t acc, float16x4_t lhs, float16
}

// CHECK-LABEL: @test_vcmlaq_rot90_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
// CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot90_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_rot90_lane_f16(acc, lhs, rhs, 1);
Expand Down Expand Up @@ -319,10 +315,8 @@ float16x4_t test_vcmla_rot180_laneq_f16(float16x4_t acc, float16x4_t lhs, float1
}

// CHECK-LABEL: @test_vcmlaq_rot180_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
// CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot180_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_rot180_lane_f16(acc, lhs, rhs, 1);
Expand Down Expand Up @@ -395,10 +389,8 @@ float16x4_t test_vcmla_rot270_laneq_f16(float16x4_t acc, float16x4_t lhs, float1
}

// CHECK-LABEL: @test_vcmlaq_rot270_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
// CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot270_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_rot270_lane_f16(acc, lhs, rhs, 1);
Expand Down

0 comments on commit 32a9c09

Please sign in to comment.