[SVE] Lower fixed length VECREDUCE_OR operation

Differential Revision: https://reviews.llvm.org/D88847
llvm · Oct 7, 2020 · 333b2ab · 333b2ab
1 parent fc819b6
commit 333b2ab
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diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1121,6 +1121,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::VECREDUCE_AND, MVT::v2i32, Custom);
       setOperationAction(ISD::VECREDUCE_AND, MVT::v4i32, Custom);
       setOperationAction(ISD::VECREDUCE_AND, MVT::v2i64, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::v8i8, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::v16i8, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::v4i16, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::v8i16, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::v2i32, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::v4i32, Custom);
+      setOperationAction(ISD::VECREDUCE_OR, MVT::v2i64, Custom);
       setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
       setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
       setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
@@ -1263,6 +1270,7 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
   setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
   setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
   setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
+  setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
   setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
   setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
   setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
@@ -3944,6 +3952,7 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
     return LowerSTORE(Op, DAG);
   case ISD::VECREDUCE_ADD:
   case ISD::VECREDUCE_AND:
+  case ISD::VECREDUCE_OR:
   case ISD::VECREDUCE_SMAX:
   case ISD::VECREDUCE_SMIN:
   case ISD::VECREDUCE_UMAX:
@@ -9732,6 +9741,7 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
   // Try to lower fixed length reductions to SVE.
   EVT SrcVT = Src.getValueType();
   bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND ||
+                      Op.getOpcode() == ISD::VECREDUCE_OR ||
                       (Op.getOpcode() != ISD::VECREDUCE_ADD &&
                        SrcVT.getVectorElementType() == MVT::i64);
   if (useSVEForFixedLengthVectorVT(SrcVT, OverrideNEON)) {
@@ -9740,6 +9750,8 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
       return LowerFixedLengthReductionToSVE(AArch64ISD::UADDV_PRED, Op, DAG);
     case ISD::VECREDUCE_AND:
       return LowerFixedLengthReductionToSVE(AArch64ISD::ANDV_PRED, Op, DAG);
+    case ISD::VECREDUCE_OR:
+      return LowerFixedLengthReductionToSVE(AArch64ISD::ORV_PRED, Op, DAG);
     case ISD::VECREDUCE_SMAX:
       return LowerFixedLengthReductionToSVE(AArch64ISD::SMAXV_PRED, Op, DAG);
     case ISD::VECREDUCE_SMIN: