[mips] Fix expanding lw/sw $reg1, symbol($reg2) instruction

When a "base" in the `lw/sw $reg1, symbol($reg2)` instruction is
a register and generated code is position independent, backend
does not add the "base" value to the symbol address.
```
lw     $reg1, %got(symbol)($gp)
lw/sw  $reg1, 0($reg1)
```

This patch fixes the bug and adds the missed `addu` instruction by
passing `BaseReg` into the `loadAndAddSymbolAddress` routine and handles
the case when the `BaseReg` is the zero register to escape redundant
`move reg, reg` instruction:
```
lw     $reg1, %got(symbol)($gp)
addu   $reg1, $reg1, $reg2
lw/sw  $reg1, 0($reg1)
```

Differential Revision: https://reviews.llvm.org/D66894

llvm-svn: 370353

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

@@ -2870,7 +2870,8 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
                                             const MCSubtargetInfo *STI) {
   // FIXME: These expansions do not respect -mxgot.
   MipsTargetStreamer &TOut = getTargetStreamer();
-  bool UseSrcReg = SrcReg != Mips::NoRegister;
+  bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO &&
+                   SrcReg != Mips::ZERO_64;
   warnIfNoMacro(IDLoc);
 
   if (inPicMode() && ABI.IsO32()) {
@@ -3654,7 +3655,6 @@ void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   if (OffsetOp.isExpr()) {
     if (inPicMode()) {
       // FIXME:
-      // a) Fix lw/sw $reg, symbol($reg) instruction expanding.
       // c) Check that immediates of R_MIPS_GOT16/R_MIPS_LO16 relocations
       //    do not exceed 16-bit.
       // d) Use R_MIPS_GOT_PAGE/R_MIPS_GOT_OFST relocations instead
@@ -3670,7 +3670,7 @@ void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
         return;
       }
 
-      loadAndAddSymbolAddress(Res.getSymA(), TmpReg, Mips::NoRegister,
+      loadAndAddSymbolAddress(Res.getSymA(), TmpReg, BaseReg,
                               !ABI.ArePtrs64bit(), IDLoc, Out, STI);
       TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, Res.getConstant(), IDLoc,
                    STI);

llvm/test/MC/Mips/mips-expansions.s

@@ -112,13 +112,13 @@
   lw $10, symbol($4)
 # CHECK-LE: lw      $10, %got(symbol)($gp)    # encoding: [A,A,0x8a,0x8f]
 # CHECK-LE:                                   #   fixup A - offset: 0, value: %got(symbol), kind: fixup_Mips_GOT
-# CHECK-LE-FIXME: addu    $10, $10, $4        # encoding: [0x21,0x50,0x44,0x01]
+# CHECK-LE: addu    $10, $10, $4              # encoding: [0x21,0x50,0x44,0x01]
 # CHECK-LE: lw      $10, 0($10)               # encoding: [0x00,0x00,0x4a,0x8d]
   .set at
   sw $10, symbol($9)
 # CHECK-LE: lw      $1, %got(symbol)($gp)     # encoding: [A,A,0x81,0x8f]
 # CHECK-LE:                                   #   fixup A - offset: 0, value: %got(symbol), kind: fixup_Mips_GOT
-# CHECK-LE-FIXME: addu    $1, $1, $9          # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: addu    $1, $1, $9                # encoding: [0x21,0x08,0x29,0x00]
 # CHECK-LE: sw      $10, 0($1)                # encoding: [0x00,0x00,0x2a,0xac]
 
   lw $8, 1f+8

llvm/test/MC/Mips/mips64-expansions.s

@@ -472,12 +472,12 @@ sym:
   lw $10, symbol($4)
 # CHECK: ld      $10, %got_disp(symbol)($gp) # encoding: [A,A,0x8a,0xdf]
 # CHECK:                                    #   fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
-# CHECK-FIXME: daddu   $10, $10, $4         # encoding: [0x2d,0x50,0x44,0x01]
+# CHECK: daddu   $10, $10, $4               # encoding: [0x2d,0x50,0x44,0x01]
 # CHECK: lw      $10, 0($10)                # encoding: [0x00,0x00,0x4a,0x8d]
   sw $10, symbol($9)
 # CHECK: ld      $1, %got_disp(symbol)($gp) # encoding: [A,A,0x81,0xdf]
 # CHECK:                                    #   fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
-# CHECK-FIXME: daddu    $1, $1, $9          # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: daddu   $1, $1, $9                 # encoding: [0x2d,0x08,0x29,0x00]
 # CHECK: sw      $10, 0($1)                 # encoding: [0x00,0x00,0x2a,0xac]
 
   lw $8, sym+8