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[RISCV][GISel] Fix failure to legalize non-power of 2 shifts between …
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…i32 and i64 on RV64.

We weren't legalizing the shift amount to i64.
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topperc committed Oct 25, 2023
1 parent f9306f6 commit 35d771f
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Showing 4 changed files with 85 additions and 1 deletion.
3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
.legalFor({{s32, s32}, {XLenLLT, XLenLLT}})
.widenScalarToNextPow2(0)
.clampScalar(1, s32, XLenLLT)
.clampScalar(0, s32, XLenLLT);
.clampScalar(0, s32, XLenLLT)
.minScalarSameAs(1, 0);

if (ST.is64Bit()) {
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
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Original file line number Diff line number Diff line change
Expand Up @@ -359,3 +359,32 @@ body: |
PseudoRET implicit $x10, implicit $x11, implicit $x12
...
---
name: ashr_i48
body: |
bb.0:
liveins: $x10, $x11
; CHECK-LABEL: name: ashr_i48
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
%0:_(s48) = G_TRUNC %2(s64)
%3:_(s64) = COPY $x11
%1:_(s48) = G_TRUNC %3(s64)
%4:_(s48) = G_ASHR %0, %1(s48)
%5:_(s64) = G_ANYEXT %4(s48)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
Original file line number Diff line number Diff line change
Expand Up @@ -352,3 +352,31 @@ body: |
PseudoRET implicit $x10, implicit $x11, implicit $x12
...
---
name: lshr_i48
body: |
bb.0:
liveins: $x10, $x11
; CHECK-LABEL: name: lshr_i48
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[AND1]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
%0:_(s48) = G_TRUNC %2(s64)
%3:_(s64) = COPY $x11
%1:_(s48) = G_TRUNC %3(s64)
%4:_(s48) = G_LSHR %0, %1(s48)
%5:_(s64) = G_ANYEXT %4(s48)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
26 changes: 26 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir
Original file line number Diff line number Diff line change
Expand Up @@ -310,3 +310,29 @@ body: |
PseudoRET implicit $x10, implicit $x11, implicit $x12
...
---
name: shl_i48
body: |
bb.0:
liveins: $x10, $x11
; CHECK-LABEL: name: shl_i48
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%2:_(s64) = COPY $x10
%0:_(s48) = G_TRUNC %2(s64)
%3:_(s64) = COPY $x11
%1:_(s48) = G_TRUNC %3(s64)
%4:_(s48) = G_SHL %0, %1(s48)
%5:_(s64) = G_ANYEXT %4(s48)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...

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