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[AArch64] Pre-commit some tests for D152828 (NFC)
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Generate a few of the relevant tests with `update_llc_test_checks.py`
and pre-commit. Makes it easier to spot the differences in D152828.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D157116
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@momchil-velikov
momchil-velikov committed Sep 21, 2023
1 parent 0eb0a65 commit 3769aaa
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Showing 4 changed files with 538 additions and 73 deletions.
140 changes: 81 additions & 59 deletions llvm/test/CodeGen/AArch64/arm64-stp.ll
View file
Original file line number Diff line number Diff line change
@@ -1,44 +1,55 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-enable-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s

; CHECK-LABEL: stp_int
; CHECK: stp w0, w1, [x2]
define void @stp_int(i32 %a, i32 %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stp_int:
; CHECK: // %bb.0:
; CHECK-NEXT: stp w0, w1, [x2]
; CHECK-NEXT: ret
store i32 %a, ptr %p, align 4
%add.ptr = getelementptr inbounds i32, ptr %p, i64 1
store i32 %b, ptr %add.ptr, align 4
ret void
}

; CHECK-LABEL: stp_long
; CHECK: stp x0, x1, [x2]
define void @stp_long(i64 %a, i64 %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stp_long:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x0, x1, [x2]
; CHECK-NEXT: ret
store i64 %a, ptr %p, align 8
%add.ptr = getelementptr inbounds i64, ptr %p, i64 1
store i64 %b, ptr %add.ptr, align 8
ret void
}

; CHECK-LABEL: stp_float
; CHECK: stp s0, s1, [x0]
define void @stp_float(float %a, float %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stp_float:
; CHECK: // %bb.0:
; CHECK-NEXT: stp s0, s1, [x0]
; CHECK-NEXT: ret
store float %a, ptr %p, align 4
%add.ptr = getelementptr inbounds float, ptr %p, i64 1
store float %b, ptr %add.ptr, align 4
ret void
}

; CHECK-LABEL: stp_double
; CHECK: stp d0, d1, [x0]
define void @stp_double(double %a, double %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stp_double:
; CHECK: // %bb.0:
; CHECK-NEXT: stp d0, d1, [x0]
; CHECK-NEXT: ret
store double %a, ptr %p, align 8
%add.ptr = getelementptr inbounds double, ptr %p, i64 1
store double %b, ptr %add.ptr, align 8
ret void
}

; CHECK-LABEL: stp_doublex2
; CHECK: stp q0, q1, [x0]
define void @stp_doublex2(<2 x double> %a, <2 x double> %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stp_doublex2:
; CHECK: // %bb.0:
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
store <2 x double> %a, ptr %p, align 16
%add.ptr = getelementptr inbounds <2 x double>, ptr %p, i64 1
store <2 x double> %b, ptr %add.ptr, align 16
Expand All @@ -47,9 +58,10 @@ define void @stp_doublex2(<2 x double> %a, <2 x double> %b, ptr nocapture %p) no

; Test the load/store optimizer---combine ldurs into a ldp, if appropriate
define void @stur_int(i32 %a, i32 %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stur_int
; CHECK: stp w{{[0-9]+}}, {{w[0-9]+}}, [x{{[0-9]+}}, #-8]
; CHECK-NEXT: ret
; CHECK-LABEL: stur_int:
; CHECK: // %bb.0:
; CHECK-NEXT: stp w1, w0, [x2, #-8]
; CHECK-NEXT: ret
%p1 = getelementptr inbounds i32, ptr %p, i32 -1
store i32 %a, ptr %p1, align 2
%p2 = getelementptr inbounds i32, ptr %p, i32 -2
Expand All @@ -58,9 +70,10 @@ define void @stur_int(i32 %a, i32 %b, ptr nocapture %p) nounwind {
}

define void @stur_long(i64 %a, i64 %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stur_long
; CHECK: stp x{{[0-9]+}}, {{x[0-9]+}}, [x{{[0-9]+}}, #-16]
; CHECK-NEXT: ret
; CHECK-LABEL: stur_long:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x1, x0, [x2, #-16]
; CHECK-NEXT: ret
%p1 = getelementptr inbounds i64, ptr %p, i32 -1
store i64 %a, ptr %p1, align 2
%p2 = getelementptr inbounds i64, ptr %p, i32 -2
Expand All @@ -69,9 +82,10 @@ define void @stur_long(i64 %a, i64 %b, ptr nocapture %p) nounwind {
}

define void @stur_float(float %a, float %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stur_float
; CHECK: stp s{{[0-9]+}}, {{s[0-9]+}}, [x{{[0-9]+}}, #-8]
; CHECK-NEXT: ret
; CHECK-LABEL: stur_float:
; CHECK: // %bb.0:
; CHECK-NEXT: stp s1, s0, [x0, #-8]
; CHECK-NEXT: ret
%p1 = getelementptr inbounds float, ptr %p, i32 -1
store float %a, ptr %p1, align 2
%p2 = getelementptr inbounds float, ptr %p, i32 -2
Expand All @@ -80,9 +94,10 @@ define void @stur_float(float %a, float %b, ptr nocapture %p) nounwind {
}

define void @stur_double(double %a, double %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stur_double
; CHECK: stp d{{[0-9]+}}, {{d[0-9]+}}, [x{{[0-9]+}}, #-16]
; CHECK-NEXT: ret
; CHECK-LABEL: stur_double:
; CHECK: // %bb.0:
; CHECK-NEXT: stp d1, d0, [x0, #-16]
; CHECK-NEXT: ret
%p1 = getelementptr inbounds double, ptr %p, i32 -1
store double %a, ptr %p1, align 2
%p2 = getelementptr inbounds double, ptr %p, i32 -2
Expand All @@ -91,9 +106,10 @@ define void @stur_double(double %a, double %b, ptr nocapture %p) nounwind {
}

define void @stur_doublex2(<2 x double> %a, <2 x double> %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stur_doublex2
; CHECK: stp q{{[0-9]+}}, q{{[0-9]+}}, [x{{[0-9]+}}, #-32]
; CHECK-NEXT: ret
; CHECK-LABEL: stur_doublex2:
; CHECK: // %bb.0:
; CHECK-NEXT: stp q1, q0, [x0, #-32]
; CHECK-NEXT: ret
%p1 = getelementptr inbounds <2 x double>, ptr %p, i32 -1
store <2 x double> %a, ptr %p1, align 2
%p2 = getelementptr inbounds <2 x double>, ptr %p, i32 -2
Expand All @@ -102,13 +118,12 @@ define void @stur_doublex2(<2 x double> %a, <2 x double> %b, ptr nocapture %p) n
}

define void @splat_v4i32(i32 %v, ptr %p) {
; CHECK-LABEL: splat_v4i32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: dup v0.4s, w0
; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret
entry:

; CHECK-LABEL: splat_v4i32
; CHECK-DAG: dup v0.4s, w0
; CHECK-DAG: str q0, [x1]
; CHECK: ret

%p17 = insertelement <4 x i32> undef, i32 %v, i32 0
%p18 = insertelement <4 x i32> %p17, i32 %v, i32 1
%p19 = insertelement <4 x i32> %p18, i32 %v, i32 2
Expand All @@ -120,17 +135,22 @@ entry:
; Check that a non-splat store that is storing a vector created by 4
; insertelements that is not a splat vector does not get split.
define void @nosplat_v4i32(i32 %v, ptr %p) {
entry:

; CHECK-LABEL: nosplat_v4i32:
; CHECK: str w0,
; CHECK: ldr q[[REG1:[0-9]+]],
; CHECK-DAG: mov v[[REG1]].s[1], w0
; CHECK-DAG: mov v[[REG1]].s[2], w0
; CHECK-DAG: mov v[[REG1]].s[3], w0
; CHECK: str q[[REG1]], [x1]
; CHECK: ret

; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: bfi x8, x0, #2, #2
; CHECK-NEXT: str w0, [x8]
; CHECK-NEXT: ldr q0, [sp]
; CHECK-NEXT: mov v0.s[1], w0
; CHECK-NEXT: mov v0.s[2], w0
; CHECK-NEXT: mov v0.s[3], w0
; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
entry:
%p17 = insertelement <4 x i32> undef, i32 %v, i32 %v
%p18 = insertelement <4 x i32> %p17, i32 %v, i32 1
%p19 = insertelement <4 x i32> %p18, i32 %v, i32 2
Expand All @@ -142,15 +162,14 @@ entry:
; Check that a non-splat store that is storing a vector created by 4
; insertelements that is not a splat vector does not get split.
define void @nosplat2_v4i32(i32 %v, ptr %p, <4 x i32> %vin) {
entry:

; CHECK-LABEL: nosplat2_v4i32:
; CHECK: mov v[[REG1]].s[1], w0
; CHECK-DAG: mov v[[REG1]].s[2], w0
; CHECK-DAG: mov v[[REG1]].s[3], w0
; CHECK: str q[[REG1]], [x1]
; CHECK: ret

; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.s[1], w0
; CHECK-NEXT: mov v0.s[2], w0
; CHECK-NEXT: mov v0.s[3], w0
; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret
entry:
%p18 = insertelement <4 x i32> %vin, i32 %v, i32 1
%p19 = insertelement <4 x i32> %p18, i32 %v, i32 2
%p20 = insertelement <4 x i32> %p19, i32 %v, i32 3
Expand All @@ -159,12 +178,14 @@ entry:
}

; Read of %b to compute %tmp2 shouldn't prevent formation of stp
; CHECK-LABEL: stp_int_rar_hazard
; CHECK: ldr [[REG:w[0-9]+]], [x2, #8]
; CHECK: add w8, [[REG]], w1
; CHECK: stp w0, w1, [x2]
; CHECK: ret
define i32 @stp_int_rar_hazard(i32 %a, i32 %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stp_int_rar_hazard:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x2, #8]
; CHECK-NEXT: add w8, w8, w1
; CHECK-NEXT: stp w0, w1, [x2]
; CHECK-NEXT: mov x0, x8
; CHECK-NEXT: ret
store i32 %a, ptr %p, align 4
%ld.ptr = getelementptr inbounds i32, ptr %p, i64 2
%tmp = load i32, ptr %ld.ptr, align 4
Expand All @@ -175,12 +196,13 @@ define i32 @stp_int_rar_hazard(i32 %a, i32 %b, ptr nocapture %p) nounwind {
}

; Read of %b to compute %tmp2 shouldn't prevent formation of stp
; CHECK-LABEL: stp_int_rar_hazard_after
; CHECK: ldr [[REG:w[0-9]+]], [x3, #4]
; CHECK: add w0, [[REG]], w2
; CHECK: stp w1, w2, [x3]
; CHECK: ret
define i32 @stp_int_rar_hazard_after(i32 %w0, i32 %a, i32 %b, ptr nocapture %p) nounwind {
; CHECK-LABEL: stp_int_rar_hazard_after:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x3, #4]
; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: stp w1, w2, [x3]
; CHECK-NEXT: ret
store i32 %a, ptr %p, align 4
%ld.ptr = getelementptr inbounds i32, ptr %p, i64 1
%tmp = load i32, ptr %ld.ptr, align 4
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/optimize-imm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ entry:
define i32 @and4(i32 %a) {
; CHECK-LABEL: and4:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #61951
; CHECK-NEXT: mov w8, #61951 // =0xf1ff
; CHECK-NEXT: and w9, w0, #0xfffc07ff
; CHECK-NEXT: movk w8, #65521, lsl #16
; CHECK-NEXT: orr w0, w9, w8
Expand All @@ -61,7 +61,7 @@ entry:
define i32 @xor1(i32 %a) {
; CHECK-LABEL: xor1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #56
; CHECK-NEXT: mov w8, #56 // =0x38
; CHECK-NEXT: bic w0, w8, w0, lsl #3
; CHECK-NEXT: ret
entry:
Expand All @@ -78,9 +78,9 @@ define i64 @PR33100(i64 %arg) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: mov w8, #129
; CHECK-NEXT: mov w8, #129 // =0x81
; CHECK-NEXT: eor x0, x0, x8
; CHECK-NEXT: mov w8, #8
; CHECK-NEXT: mov w8, #8 // =0x8
; CHECK-NEXT: str x8, [sp, #8]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
Expand Down
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