Skip to content

Commit

Permalink
[RISCV][GISel] First mask argument placed in v0 according to RISCV Ve… (
Browse files Browse the repository at this point in the history 
#79343)

…ctor CC.
  • Loading branch information
@michaelmaitland
michaelmaitland committed Jan 24, 2024
1 parent 6e4930c commit 3967510
Show file tree
Hide file tree
Showing 3 changed files with 138 additions and 60 deletions.
26 changes: 22 additions & 4 deletions llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,9 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
// Whether this is assigning args for a return.
bool IsRet;

// true if assignArg has been called for a mask argument, false otherwise.
bool AssignedFirstMaskArg = false;

public:
RISCVOutgoingValueAssigner(
RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
Expand All @@ -48,10 +51,16 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
const DataLayout &DL = MF.getDataLayout();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();

std::optional<unsigned> FirstMaskArgument;
if (Subtarget.hasVInstructions() && !AssignedFirstMaskArg &&
ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1) {
FirstMaskArgument = ValNo;
AssignedFirstMaskArg = true;
}

if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty,
*Subtarget.getTargetLowering(),
/*FirstMaskArgument=*/std::nullopt))
*Subtarget.getTargetLowering(), FirstMaskArgument))
return true;

StackSize = State.getStackSize();
Expand Down Expand Up @@ -172,6 +181,9 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
// Whether this is assigning args from a return.
bool IsRet;

// true if assignArg has been called for a mask argument, false otherwise.
bool AssignedFirstMaskArg = false;

public:
RISCVIncomingValueAssigner(
RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
Expand All @@ -189,10 +201,16 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
if (LocVT.isScalableVector())
MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();

std::optional<unsigned> FirstMaskArgument;
if (Subtarget.hasVInstructions() && !AssignedFirstMaskArg &&
ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1) {
FirstMaskArgument = ValNo;
AssignedFirstMaskArg = true;
}

if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty,
*Subtarget.getTargetLowering(),
/*FirstMaskArgument=*/std::nullopt))
*Subtarget.getTargetLowering(), FirstMaskArgument))
return true;

StackSize = State.getStackSize();
Expand Down
116 changes: 88 additions & 28 deletions llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-args.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -407,16 +407,16 @@ entry:
define void @test_args_nxv64i1(<vscale x 64 x i1> %a) {
; RV32-LABEL: name: test_args_nxv64i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v8
; RV32-NEXT: liveins: $v0
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv64i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v8
; RV64-NEXT: liveins: $v0
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
Expand All @@ -425,16 +425,16 @@ entry:
define void @test_args_nxv32i1(<vscale x 32 x i1> %a) {
; RV32-LABEL: name: test_args_nxv32i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v8
; RV32-NEXT: liveins: $v0
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv32i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v8
; RV64-NEXT: liveins: $v0
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
Expand All @@ -443,16 +443,16 @@ entry:
define void @test_args_nxv16i1(<vscale x 16 x i1> %a) {
; RV32-LABEL: name: test_args_nxv16i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v8
; RV32-NEXT: liveins: $v0
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv16i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v8
; RV64-NEXT: liveins: $v0
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
Expand All @@ -461,16 +461,16 @@ entry:
define void @test_args_nxv8i1(<vscale x 8 x i1> %a) {
; RV32-LABEL: name: test_args_nxv8i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v8
; RV32-NEXT: liveins: $v0
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv8i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v8
; RV64-NEXT: liveins: $v0
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
Expand All @@ -479,16 +479,16 @@ entry:
define void @test_args_nxv4i1(<vscale x 4 x i1> %a) {
; RV32-LABEL: name: test_args_nxv4i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v8
; RV32-NEXT: liveins: $v0
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv4i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v8
; RV64-NEXT: liveins: $v0
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
Expand All @@ -497,16 +497,16 @@ entry:
define void @test_args_nxv2i1(<vscale x 2 x i1> %a) {
; RV32-LABEL: name: test_args_nxv2i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v8
; RV32-NEXT: liveins: $v0
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv2i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v8
; RV64-NEXT: liveins: $v0
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
Expand All @@ -515,16 +515,16 @@ entry:
define void @test_args_nxv1i1(<vscale x 1 x i1> %a) {
; RV32-LABEL: name: test_args_nxv1i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v8
; RV32-NEXT: liveins: $v0
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv1i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v8
; RV64-NEXT: liveins: $v0
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
Expand Down Expand Up @@ -907,3 +907,63 @@ define void @test_args_nxv32b16(<vscale x 32 x bfloat> %a) {
entry:
ret void
}

define void @test_args_nxv1i1_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
; RV32-LABEL: name: test_args_nxv1i1_nxv1i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v0, $v8
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv1i1_nxv1i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v0, $v8
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
}

define void @test_args_nxv1i1_nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b) {
; RV32-LABEL: name: test_args_nxv1i1_nxv1i32
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v0, $v8
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv1i1_nxv1i32
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v0, $v8
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
; RV64-NEXT: PseudoRET
entry:
ret void
}

define void @test_args_nxv1i32_nxv1i1(<vscale x 1 x i32> %a, <vscale x 1 x i1> %b) {
; RV32-LABEL: name: test_args_nxv1i32_nxv1i1
; RV32: bb.1.entry:
; RV32-NEXT: liveins: $v0, $v8
; RV32-NEXT: {{ $}}
; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV32-NEXT: PseudoRET
;
; RV64-LABEL: name: test_args_nxv1i32_nxv1i1
; RV64: bb.1.entry:
; RV64-NEXT: liveins: $v0, $v8
; RV64-NEXT: {{ $}}
; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8
; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
; RV64-NEXT: PseudoRET
entry:
ret void
}

0 comments on commit 3967510

Please sign in to comment.