[mips] Promote the result of SETCC nodes to GPR width.

Summary:
This patch modifies the existing comparison, branch, conditional-move
and select patterns, and adds new ones where needed. Also, the updated
SLT{u,i,iu} set of instructions generate a GPR width result.

The majority of the code changes in the Mips back-end fix the wrong
assumption that the result of SETCC nodes always produce an i32 value.
The changes in the common code path account for the fact that in 64-bit
MIPS targets, i1 is promoted to i32 instead of i64.

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D10970

llvm-svn: 262316

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -14151,8 +14151,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
           Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
                                         N2.getValueType());
         else
-          Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
-                             N2.getValueType(), SCC);
+          Temp = DAG.getZExtOrTrunc(SCC, SDLoc(N2), N2.getValueType());
       } else {
         SCC  = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
         Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

@@ -520,7 +520,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
 /// Promote the overflow flag of an overflowing arithmetic node.
 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
   // Simply change the return type of the boolean result.
-  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
+  EVT NVT = getSetCCResultType(N->getValueType(1));
   EVT ValueVTs[] = { N->getValueType(0), NVT };
   SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
   SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

@@ -750,8 +750,9 @@ void DAGTypeLegalizer::ReplaceValueWith(SDValue From, SDValue To) {
 }
 
 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
-  assert(Result.getValueType() ==
-         TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
+  assert(((Result.getValueType() ==
+           TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType())) ||
+          (Result.getValueType() == getSetCCResultType(Op.getValueType()))) &&
          "Invalid type for promoted integer");
   AnalyzeNewValue(Result);
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -3656,6 +3656,9 @@ void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
 }
 
 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  LLVMContext &Ctx = *DAG.getContext();
+
   SDLoc dl = getCurSDLoc();
   AtomicOrdering SuccessOrder = I.getSuccessOrdering();
   AtomicOrdering FailureOrder = I.getFailureOrdering();
@@ -3664,7 +3667,14 @@ void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
   SDValue InChain = getRoot();
 
   MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
-  SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
+  EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), Ctx, MVT::i1);
+
+  // Only use the result of getSetCCResultType if it is legal,
+  // otherwise just use the promoted result type (NVT).
+  if (!TLI.isTypeLegal(CCVT))
+    CCVT = TLI.getTypeToTransformTo(Ctx, MVT::i1);
+
+  SDVTList VTs = DAG.getVTList(MemVT, CCVT, MVT::Other);
   SDValue L = DAG.getAtomicCmpSwap(
       ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
       getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),

llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

@@ -124,9 +124,13 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
                                            uint64_t Address,
                                            const void *Decoder);
 
-static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
-                                             uint64_t Address,
-                                             const void *Decoder);
+static DecodeStatus DecodeFGRCC32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder);
+
+static DecodeStatus DecodeFGRCC64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder);
 
 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
                                               unsigned Insn,
@@ -898,6 +902,17 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
     if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
 
+    if (hasMips32r6() && isGP64()) {
+      DEBUG(dbgs() << "Trying MicroMipsR6_GP64 table (32-bit instructions):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableMicroMipsR6_GP6432, Instr, Insn,
+                                 Address, this, STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
     if (hasMips32r6()) {
       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
       // Calling the auto-generated decoder function.
@@ -940,9 +955,9 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   }
 
   if (hasMips32r6() && isGP64()) {
-    DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
-    Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
-                               Address, this, STI);
+    DEBUG(dbgs() << "Trying Mips64r6 (GPR64) table (32-bit opcodes):\n");
+    Result = decodeInstruction(DecoderTableMips64r632, Instr, Insn, Address,
+                               this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
@@ -1121,13 +1136,24 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
-                                             uint64_t Address,
-                                             const void *Decoder) {
+static DecodeStatus DecodeFGRCC32RegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+
+  unsigned Reg = getReg(Decoder, Mips::FGRCC32RegClassID, RegNo);
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFGRCC64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                               uint64_t Address,
+                                               const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
-  unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
+  unsigned Reg = getReg(Decoder, Mips::FGRCC64RegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

@@ -634,71 +634,71 @@ class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
                                              II_CVT>, FGR_64;
 
 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
-                       RegisterOperand FGROpnd> {
+                       RegisterOperand FGRCCOpnd, RegisterOperand FGROpnd> {
   def CMP_AF_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
-      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"af", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_UN_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
-      CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"un", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_EQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
-      CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"eq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
-      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_LT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
-      CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"lt", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_ULT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
-      CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"ult", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_LE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
-      CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"le", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_ULE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
-      CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"ule", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SAF_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
-      CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"saf", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SUN_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
-      CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sun", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
-      CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"seq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
-      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SLT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
-      CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"slt", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SULT_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
-      CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sult", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SLE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
-      CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sle", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
   def CMP_SULE_#NAME : POOL32F_CMP_FM<
       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
-      CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
-      ISA_MICROMIPS32R6;
+      CMP_CONDN_DESC_BASE<"sule", Typestr, FGRCCOpnd, FGROpnd>,
+      HARDFLOAT, R6MMR6Rel, ISA_MICROMIPS32R6;
 }
 
 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
@@ -763,8 +763,8 @@ class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
                                                    FGR64Opnd, II_ROUND>;
 
-class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
-class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
+class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC32Opnd, FGR32Opnd>;
+class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC32Opnd, FGR64Opnd> {
   // We must insert a SUBREG_TO_REG around $fd_in
   bit usesCustomInserter = 1;
 }
@@ -1115,8 +1115,8 @@ def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
                    ISA_MICROMIPS32R6;
-defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
-defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
+defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGRCC32Opnd, FGR32Opnd>;
+defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGRCC32Opnd, FGR64Opnd>;
 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
@@ -1200,8 +1200,10 @@ def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;
 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
                      ISA_MICROMIPS32R6;
-def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
-def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
+def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6,
+                 HARDFLOAT;
+def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6,
+                 HARDFLOAT;
 def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
                     ISA_MICROMIPS32R6;
 def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,

llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td

@@ -99,6 +99,12 @@ class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
 class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
                                  MipsIns>;
 
+class SEL_S_MM64R6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGRCC64Opnd, FGR32Opnd> {
+  // We must copy FGRCC64Opnd's subreg into FGR32.
+  bit usesCustomInserter = 1;
+}
+class SEL_D_MM64R6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGRCC64Opnd, FGR64Opnd>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
@@ -132,3 +138,10 @@ let DecoderNamespace = "MicroMipsR6" in {
   def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
                    ISA_MICROMIPS64R6;
 }
+
+let DecoderNamespace = "MicroMipsR6_GP64" in {
+def SEL_S_MM64R6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MM64R6_DESC,
+                   ISA_MICROMIPS64R6, HARDFLOAT;
+def SEL_D_MM64R6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MM64R6_DESC,
+                   ISA_MICROMIPS64R6, HARDFLOAT;
+}

llvm/lib/Target/Mips/MicroMipsInstrInfo.td

@@ -671,10 +671,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
                  ADDI_FM_MM<0xc>;
   def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
                  ADDI_FM_MM<0x4>;
-  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
-                 SLTI_FM_MM<0x24>;
-  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
-                 SLTI_FM_MM<0x2c>;
+  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd,
+                                GPR32Opnd>, SLTI_FM_MM<0x24>;
+  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd,
+                                GPR32Opnd>, SLTI_FM_MM<0x2c>;
   def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
                  ADDI_FM_MM<0x34>;
   def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
@@ -694,8 +694,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
   def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
   def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
-  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
-  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
+  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd, GPR32Opnd>,
+                 ADD_FM_MM<0, 0x350>;
+  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd, GPR32Opnd>,
                  ADD_FM_MM<0, 0x390>;
   def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
                  ADD_FM_MM<0, 0x250>;