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TargetMachine: Merge TargetMachine and LLVMTargetMachine
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Merge LLVMTargetMachine into TargetMachine.

- There is no in-tree target anymore that just implements TargetMachine
  but not LLVMTargetMachine.
- It should still be possible to stub out all the various functions in
  case a target does not want to use lib/CodeGen
- This simplifies the code and avoids methods ending up in the wrong
  interface.

Differential Revision: https://reviews.llvm.org/D38489

llvm-svn: 315633
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MatzeB committed Oct 12, 2017
1 parent 150b7d6 commit 3a9c114
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Showing 52 changed files with 296 additions and 408 deletions.
7 changes: 3 additions & 4 deletions llvm/include/llvm/CodeGen/TargetPassConfig.h
Expand Up @@ -21,10 +21,10 @@

namespace llvm {

class LLVMTargetMachine;
struct MachineSchedContext;
class PassConfigImpl;
class ScheduleDAGInstrs;
class TargetMachine;

// The old pass manager infrastructure is hidden in a legacy namespace now.
namespace legacy {
Expand Down Expand Up @@ -121,7 +121,7 @@ class TargetPassConfig : public ImmutablePass {
void setStartStopPasses();

protected:
LLVMTargetMachine *TM;
TargetMachine *TM;
PassConfigImpl *Impl = nullptr; // Internal data structures
bool Initialized = false; // Flagged after all passes are configured.

Expand All @@ -141,7 +141,7 @@ class TargetPassConfig : public ImmutablePass {
bool addCoreISelPasses();

public:
TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
TargetPassConfig(TargetMachine &TM, PassManagerBase &pm);
// Dummy constructor.
TargetPassConfig();

Expand Down Expand Up @@ -378,7 +378,6 @@ class TargetPassConfig : public ImmutablePass {
virtual void addFastRegAlloc(FunctionPass *RegAllocPass);

/// addOptimizedRegAlloc - Add passes related to register allocation.
/// LLVMTargetMachine provides standard regalloc passes for most targets.
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);

/// addPreRewrite - Add passes to the optimized register allocation pipeline
Expand Down
2 changes: 1 addition & 1 deletion llvm/include/llvm/MC/MCAsmInfo.h
Expand Up @@ -353,7 +353,7 @@ class MCAsmInfo {
/// The integrated assembler should be enabled by default (by the
/// constructors) when failing to parse a valid piece of assembly (inline
/// or otherwise) is considered a bug. It may then be overridden after
/// construction (see LLVMTargetMachine::initAsmInfo()).
/// construction (see TargetMachine::initAsmInfo()).
bool UseIntegratedAssembler;

/// Preserve Comments in assembly
Expand Down
65 changes: 13 additions & 52 deletions llvm/include/llvm/Target/TargetMachine.h
Expand Up @@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file defines the TargetMachine and LLVMTargetMachine classes.
/// \file Defines the TargetMachine interface.
//
//===----------------------------------------------------------------------===//

Expand Down Expand Up @@ -49,16 +49,16 @@ class PassManagerBase;
using legacy::PassManagerBase;

//===----------------------------------------------------------------------===//
///

/// Primary interface to the complete machine description for the target
/// machine. All target-specific information should be accessible through this
/// interface.
///
class TargetMachine {
protected: // Can only create subclasses.
TargetMachine(const Target &T, StringRef DataLayoutString,
const Triple &TargetTriple, StringRef CPU, StringRef FS,
const TargetOptions &Options);
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);

/// The Target that this machine was created for.
const Target &TheTarget;
Expand Down Expand Up @@ -91,6 +91,8 @@ class TargetMachine {
unsigned RequireStructuredCFG : 1;
unsigned O0WantsFastISel : 1;

void initAsmInfo();

public:
const TargetOptions DefaultOptions;
mutable TargetOptions Options;
Expand Down Expand Up @@ -225,23 +227,18 @@ class TargetMachine {
/// supported, or false on success.
/// \p MMI is an optional parameter that, if set to non-nullptr,
/// will be used to set the MachineModuloInfo for this PM.
virtual bool addPassesToEmitFile(PassManagerBase &, raw_pwrite_stream &,
CodeGenFileType,
bool /*DisableVerify*/ = true,
MachineModuleInfo *MMI = nullptr) {
return true;
}
virtual bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
CodeGenFileType FileType,
bool DisableVerify = true,
MachineModuleInfo *MMI = nullptr);

/// Add passes to the specified pass manager to get machine code emitted with
/// the MCJIT. This method returns true if machine code is not supported. It
/// fills the MCContext Ctx pointer which can be used to build custom
/// MCStreamer.
///
virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&,
raw_pwrite_stream &,
bool /*DisableVerify*/ = true) {
return true;
}
virtual bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
raw_pwrite_stream &OS,
bool DisableVerify = true);

/// True if subtarget inserts the final scheduling pass on its own.
///
Expand All @@ -265,47 +262,11 @@ class TargetMachine {
virtual bool useIPRA() const {
return false;
}
};

/// This class describes a target machine that is implemented with the LLVM
/// target-independent code generator.
///
class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
const Triple &TargetTriple, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);

void initAsmInfo();

public:
/// \brief Get a TargetIRAnalysis implementation for the target.
///
/// This analysis will produce a TTI result which uses the common code
/// generator to answer queries about the IR.
TargetIRAnalysis getTargetIRAnalysis() override;

/// Create a pass configuration object to be used by addPassToEmitX methods
/// for generating a pipeline of CodeGen passes.
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);

/// Add passes to the specified pass manager to get the specified file
/// emitted. Typically this will involve several steps of code generation.
/// \p MMI is an optional parameter that, if set to non-nullptr,
/// will be used to set the MachineModuloInfofor this PM.
bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
CodeGenFileType FileType, bool DisableVerify = true,
MachineModuleInfo *MMI = nullptr) override;

/// Add passes to the specified pass manager to get machine code emitted with
/// the MCJIT. This method returns true if machine code is not supported. It
/// fills the MCContext Ctx pointer which can be used to build custom
/// MCStreamer.
bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
raw_pwrite_stream &OS,
bool DisableVerify = true) override;

/// Returns true if the target is expected to pass all machine verifier
/// checks. This is a stopgap measure to fix targets one by one. We will
/// remove this at some point and always enable the verifier when
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/CodeGen/CMakeLists.txt
Expand Up @@ -53,7 +53,6 @@ add_llvm_library(LLVMCodeGen
LiveRegUnits.cpp
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMTargetMachine.cpp
LocalStackSlotAllocation.cpp
LowLevelType.cpp
LowerEmuTLS.cpp
Expand Down Expand Up @@ -142,6 +141,8 @@ add_llvm_library(LLVMCodeGen
TargetInstrInfo.cpp
TargetLoweringBase.cpp
TargetLoweringObjectFileImpl.cpp
TargetMachine.cpp
TargetMachineC.cpp
TargetOptionsImpl.cpp
TargetPassConfig.cpp
TargetRegisterInfo.cpp
Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/CodeGen/MachineVerifier.cpp
Expand Up @@ -17,10 +17,8 @@
// Register live intervals: Registers must be defined only once, and must be
// defined before use.
//
// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
// command-line option -verify-machineinstrs, or by defining the environment
// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
// the verifier errors.
// The machine code verifier is enabled with the command-line option
// -verify-machineinstrs.
//===----------------------------------------------------------------------===//

#include "llvm/ADT/BitVector.h"
Expand Down

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