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[SystemZ] Add support for missing instructions
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Summary:
Add support to allow clang integrated assembler to recognize some
missing instructions, for openssl.

Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.

Reviewers: uweigand

Subscribers: koriakin, llvm-commits

Differential Revision: http://reviews.llvm.org/D22050

llvm-svn: 274869
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@zhanjunl
zhanjunl committed Jul 8, 2016
1 parent 13a4583 commit 3b4c3f4
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Showing 8 changed files with 995 additions and 4 deletions.
78 changes: 74 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZInstrFormats.td
View file
Expand Up @@ -1060,12 +1060,30 @@ class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
let DisableEncoding = "$R1src";
}

class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr12only>
: InstRS<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayLoad = 1;
}

class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr20only>
: InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayLoad = 1;
}

multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
bits<16> rsyOpcode, RegisterOperand cls> {
let DispKey = mnemonic ## #cls in {
let DispSize = "12" in
def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
let DispSize = "20" in
def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
}
}

class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
: InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
mnemonic#"\t$V1, $V3, $BD2", []> {
Expand Down Expand Up @@ -1141,12 +1159,30 @@ class StoreLengthVRSb<string mnemonic, bits<16> opcode,
let AccessBytes = bytes;
}

class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr12only>
: InstRS<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayStore = 1;
}

class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
AddressingMode mode = bdaddr20only>
: InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayStore = 1;
}

multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
bits<16> rsyOpcode, RegisterOperand cls> {
let DispKey = mnemonic ## #cls in {
let DispSize = "12" in
def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
let DispSize = "20" in
def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
}
}

class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
: InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
mnemonic#"\t$V1, $V3, $BD2", []> {
Expand Down Expand Up @@ -1979,6 +2015,40 @@ class TernaryRRD<string mnemonic, bits<16> opcode,
let DisableEncoding = "$R1src";
}

class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr12only>
: InstRS<opcode, (outs cls:$R1),
(ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {

let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
}

class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
bits<5> bytes, AddressingMode mode = bdaddr20only>
: InstRSY<opcode, (outs cls:$R1),
(ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {

let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
}

multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
RegisterOperand cls, bits<5> bytes> {
let DispKey = mnemonic ## #cls in {
let DispSize = "12" in
def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
let DispSize = "20" in
def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
}
}

class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
: InstRXF<opcode, (outs cls:$R1),
Expand Down
19 changes: 19 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.td
View file
Expand Up @@ -702,10 +702,14 @@ def : StoreGR64PC<STRL, aligned_truncstorei32>;
//===----------------------------------------------------------------------===//

// Multi-register loads.
defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>;
def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>;

// Multi-register stores.
defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>;
def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>;

//===----------------------------------------------------------------------===//
// Byte swaps
Expand Down Expand Up @@ -814,6 +818,11 @@ defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;

let Defs = [CC] in {
defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>;
def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>;
}

// Insertions of a 16-bit immediate, leaving other bits unaffected.
// We don't have or_as_insert equivalents of these operations because
// OI is available instead.
Expand Down Expand Up @@ -1187,6 +1196,7 @@ def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
// Shift left.
let hasSideEffects = 0 in {
defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>;
def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
}

Expand Down Expand Up @@ -1365,6 +1375,9 @@ let Defs = [CC] in {
defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
}

def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>;
def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>;

//===----------------------------------------------------------------------===//
// Prefetch
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1648,6 +1661,12 @@ let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
"stfle\t$BD2",
[]>;

let hasSideEffects = 1 in {
def EX : InstRX<0x44, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
"ex\t$R1, $XBD2", []>;
def EXRL : InstRIL<0xC60, (outs), (ins GR64:$R1, pcrel32:$I2),
"exrl\t$R1, $I2", []>;
}


//===----------------------------------------------------------------------===//
Expand Down
32 changes: 32 additions & 0 deletions llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
View file
Expand Up @@ -1730,3 +1730,35 @@
# 0x000009d2:
# CHECK: clij %r0, 0, 15, 0x9d2
0xec 0x0f 0x00 0x00 0x00 0x7f

# 0x000009d8:
# CHECK: exrl %r0, 0x9d8
0xc6 0x00 0x00 0x00 0x00 0x00

# 0x000009de:
# CHECK: exrl %r15, 0x9de
0xc6 0xf0 0x00 0x00 0x00 0x00

# 0x000009e4:
# CHECK: exrl %r0, 0x9e2
0xc6 0x00 0xff 0xff 0xff 0xff

# 0x000009ea:
# CHECK: exrl %r15, 0x9e8
0xc6 0xf0 0xff 0xff 0xff 0xff

# 0x000009f0:
# CHECK: exrl %r0, 0xffffffff000009f0
0xc6 0x00 0x80 0x00 0x00 0x00

# 0x000009f6:
# CHECK: exrl %r15, 0xffffffff000009f6
0xc6 0xf0 0x80 0x00 0x00 0x00

# 0x000009fc:
# CHECK: exrl %r0, 0x1000009fa
0xc6 0x00 0x7f 0xff 0xff 0xff

# 0x00000a02:
# CHECK: exrl %r15, 0x100000a00
0xc6 0xf0 0x7f 0xff 0xff 0xff

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