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[NFC][AArch64] Split out backend features
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This patch splits backend features currently
hidden behind architecture versions.

For example, currently the only way to activate
complex numbers extension is targeting an v8.3
architecture, where after the patch this extension
can be added separately.

This refactoring is required by the new command lines proposal:
http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html

Reviewers: DavidSpickett, olista01, t.p.northover

Subscribers: kristof.beyls, bryanpkc, javed.absar, pbarrio

Differential revision: https://reviews.llvm.org/D54633

llvm-svn: 348121
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Diogo N. Sampaio committed Dec 3, 2018
1 parent b3301b3 commit 3c7d062
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Showing 16 changed files with 716 additions and 386 deletions.
100 changes: 95 additions & 5 deletions llvm/lib/Target/AArch64/AArch64.td
View file
Expand Up @@ -65,6 +65,18 @@ def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;

def FeaturePAN : SubtargetFeature<
"pan", "HasPAN", "true",
"Enables ARM v8.1 Privileged Access-Never extension">;

def FeatureLOR : SubtargetFeature<
"lor", "HasLOR", "true",
"Enables ARM v8.1 Limited Ordering Regions extension">;

def FeatureVH : SubtargetFeature<
"vh", "HasVH", "true",
"Enables ARM v8.1 Virtual Host extension">;

def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
"Enable ARMv8 PMUv3 Performance Monitors extension">;

Expand All @@ -77,6 +89,18 @@ def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
"Enable Statistical Profiling extension">;

def FeaturePAN_RWV : SubtargetFeature<
"pan-rwv", "HasPAN_RWV", "true",
"Enable v8.2 PAN s1e1R and s1e1W Variants",
[FeaturePAN]>;

// UAO PState
def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
"Enable v8.2 UAO PState">;

def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
"true", "Enable v8.2 data Cache Clean to Point of Persistence" >;

def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
"Enable Scalable Vector Extension (SVE) instructions">;

Expand Down Expand Up @@ -195,6 +219,66 @@ def FeatureDotProd : SubtargetFeature<
"dotprod", "HasDotProd", "true",
"Enable dot product support">;

def FeaturePA : SubtargetFeature<
"pa", "HasPA", "true",
"Enable v8.3-A Pointer Authentication enchancement">;

def FeatureJS : SubtargetFeature<
"jsconv", "HasJS", "true",
"Enable v8.3-A JavaScript FP conversion enchancement",
[FeatureFPARMv8]>;

def FeatureCCIDX : SubtargetFeature<
"ccidx", "HasCCIDX", "true",
"Enable v8.3-A Extend of the CCSIDR number of sets">;

def FeatureComplxNum : SubtargetFeature<
"complxnum", "HasComplxNum", "true",
"Enable v8.3-A Floating-point complex number support",
[FeatureNEON]>;

def FeatureNV : SubtargetFeature<
"nv", "HasNV", "true",
"Enable v8.4-A Nested Virtualization Enchancement">;

def FeatureRASv8_4 : SubtargetFeature<
"rasv8_4", "HasRASv8_4", "true",
"Enable v8.4-A Reliability, Availability and Serviceability extension",
[FeatureRAS]>;

def FeatureMPAM : SubtargetFeature<
"mpam", "HasMPAM", "true",
"Enable v8.4-A Memory system Partitioning and Monitoring extension">;

def FeatureDIT : SubtargetFeature<
"dit", "HasDIT", "true",
"Enable v8.4-A Data Independent Timing instructions">;

def FeatureTRACEV8_4 : SubtargetFeature<
"tracev8.4", "HasTRACEV8_4", "true",
"Enable v8.4-A Trace extension">;

def FeatureAM : SubtargetFeature<
"am", "HasAM", "true",
"Enable v8.4-A Activity Monitors extension">;

def FeatureSEL2 : SubtargetFeature<
"sel2", "HasSEL2", "true",
"Enable v8.4-A Secure Exception Level 2 extension">;

def FeatureTLB_RMI : SubtargetFeature<
"tlb-rmi", "HasTLB_RMI", "true",
"Enable v8.4-A TLB Range and Maintenance Instructions">;

def FeatureFMI : SubtargetFeature<
"fmi", "HasFMI", "true",
"Enable v8.4-A Flag Manipulation Instructions">;

// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
"Enable v8.4-A RCPC instructions with Immediate Offsets",
[FeatureRCPC]>;

def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
"NegativeImmediates", "false",
"Convert immediates and instructions "
Expand Down Expand Up @@ -229,7 +313,7 @@ def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
"Enable execution and data prediction invalidation instructions" >;

def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
"true", "Enable Cache Clean to Point of Deep Persistence" >;
"true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;

def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
"true", "Enable Branch Target Identification" >;
Expand All @@ -245,16 +329,22 @@ def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
//

def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
"Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
"Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
FeaturePAN, FeatureLOR, FeatureVH]>;

def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
"Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
"Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;

def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
"Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
"Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
FeatureJS, FeatureCCIDX, FeatureComplxNum]>;

def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>;
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
FeatureFMI, FeatureRCPC_IMMO]>;

def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
Expand Down
17 changes: 9 additions & 8 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
View file
Expand Up @@ -9989,9 +9989,10 @@ class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode,
let Inst{4-0} = Rd;
}

//8.3 CompNum - Floating-point complex number support
multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype,
string asm, SDPatternOperator OpNode>{
let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype,
asm, ".4h",
[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
Expand All @@ -10007,7 +10008,7 @@ multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype,
(rottype i32:$rot)))]>;
}

let Predicates = [HasV8_3a, HasNEON] in {
let Predicates = [HasComplxNum, HasNEON] in {
def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype,
asm, ".2s",
[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
Expand Down Expand Up @@ -10063,7 +10064,7 @@ class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size,
multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode,
Operand rottype, string asm,
SDPatternOperator OpNode> {
let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in {
let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64,
rottype, asm, ".4h",
[(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
Expand All @@ -10079,7 +10080,7 @@ multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode,
(rottype i32:$rot)))]>;
}

let Predicates = [HasV8_3a, HasNEON] in {
let Predicates = [HasComplxNum, HasNEON] in {
def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64,
rottype, asm, ".2s",
[(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
Expand Down Expand Up @@ -10145,7 +10146,7 @@ class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size,
// classes.
multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
string asm, SDPatternOperator OpNode> {
let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in {
let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h",
".4h", ".h", []> {
Expand All @@ -10161,17 +10162,17 @@ multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
let Inst{11} = idx{1};
let Inst{21} = idx{0};
}
} // Predicates = [HasV8_3a,HasNEON,HasFullFP16]
} // Predicates = HasComplxNum, HasNEON, HasFullFP16]

let Predicates = [HasV8_3a,HasNEON] in {
let Predicates = [HasComplxNum, HasNEON] in {
def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
V128, V128, V128, VectorIndexD, rottype, asm, ".4s",
".4s", ".4s", ".s", []> {
bits<1> idx;
let Inst{11} = idx{0};
let Inst{21} = 0;
}
} // Predicates = [HasV8_3a,HasNEON]
} // Predicates = [HasComplxNum, HasNEON]
}

//----------------------------------------------------------------------------
Expand Down
77 changes: 63 additions & 14 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Expand Up @@ -24,6 +24,54 @@ def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">,
AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;
def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,
AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;
def HasVH : Predicate<"Subtarget->hasVH()">,
AssemblerPredicate<"FeatureVH", "vh">;

def HasLOR : Predicate<"Subtarget->hasLOR()">,
AssemblerPredicate<"FeatureLOR", "lor">;

def HasPA : Predicate<"Subtarget->hasPA()">,
AssemblerPredicate<"FeaturePA", "pa">;

def HasJS : Predicate<"Subtarget->hasJS()">,
AssemblerPredicate<"FeatureJS", "jsconv">;

def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">,
AssemblerPredicate<"FeatureCCIDX", "ccidx">;

def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">,
AssemblerPredicate<"FeatureComplxNum", "complxnum">;

def HasNV : Predicate<"Subtarget->hasNV()">,
AssemblerPredicate<"FeatureNV", "nv">;

def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">,
AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">;

def HasMPAM : Predicate<"Subtarget->hasMPAM()">,
AssemblerPredicate<"FeatureMPAM", "mpam">;

def HasDIT : Predicate<"Subtarget->hasDIT()">,
AssemblerPredicate<"FeatureDIT", "dit">;

def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">,
AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">;

def HasAM : Predicate<"Subtarget->hasAM()">,
AssemblerPredicate<"FeatureAM", "am">;

def HasSEL2 : Predicate<"Subtarget->hasSEL2()">,
AssemblerPredicate<"FeatureSEL2", "sel2">;

def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,
AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">;

def HasFMI : Predicate<"Subtarget->hasFMI()">,
AssemblerPredicate<"FeatureFMI", "fmi">;

def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">,
AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">;

def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
def HasNEON : Predicate<"Subtarget->hasNEON()">,
Expand Down Expand Up @@ -510,7 +558,7 @@ def ISB : CRmSystemI<barrier_op, 0b110, "isb",
def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {
let CRm = 0b0010;
let Inst{12} = 0;
let Predicates = [HasV8_4a];
let Predicates = [HasTRACEV8_4];
}
}

Expand Down Expand Up @@ -602,7 +650,7 @@ let Uses = [LR], Defs = [LR], CRm = 0b0000 in {
}

// These pointer authentication isntructions require armv8.3a
let Predicates = [HasV8_3a] in {
let Predicates = [HasPA] in {
multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> {
def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>;
def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>;
Expand Down Expand Up @@ -642,25 +690,25 @@ let Predicates = [HasV8_3a] in {
defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>;
defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>;

// v8.3a floating point conversion for javascript
let Predicates = [HasV8_3a, HasFPARMv8] in
def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
"fjcvtzs", []> {
let Inst{31} = 0;
}
}

} // HasV8_3a
// v8.3a floating point conversion for javascript
let Predicates = [HasJS, HasFPARMv8] in
def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
"fjcvtzs", []> {
let Inst{31} = 0;
} // HasJS, HasFPARMv8

// v8.4 Flag manipulation instructions
let Predicates = [HasV8_4a] in {
let Predicates = [HasFMI] in {
def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
let Inst{20-5} = 0b0000001000000000;
}
def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">;
def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;
def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif",
"{\t$Rn, $imm, $mask}">;
} // HasV8_4a
} // HasFMI

// v8.5 flag manipulation instructions
let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {
Expand Down Expand Up @@ -2629,8 +2677,9 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",
[(truncstorei8 GPR32z:$Rt,
(am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;

// Armv8.4 LDAPR & STLR with Immediate Offset instruction
let Predicates = [HasV8_4a] in {
// Armv8.4 Weaker Release Consistency enhancements
// LDAPR & STLR with Immediate Offset instructions
let Predicates = [HasRCPC_IMMO] in {
defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>;
defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>;
defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>;
Expand Down Expand Up @@ -2915,7 +2964,7 @@ def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;

let Predicates = [HasV8_1a] in {
let Predicates = [HasLOR] in {
// v8.1a "Limited Order Region" extension load-acquire instructions
def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
Expand Down

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