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[MIPS GlobalISel] Fix mul operands
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Unsigned mul high for MIPS32 is selected into two PseudoInstructions:
PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for
some of its operands. Registers in this class have appropriate hi and lo
register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc.
mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td.
In functions where mul and PseudoMULTu are present fastRegisterAllocator
will "run out of registers during register allocation" because
'calcSpillCost' for $ac0 will return spillImpossible because subregisters
$lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is
to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction.

Differential Revision: https://reviews.llvm.org/D58715

llvm-svn: 355594
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Petar Avramovic authored and Petar Avramovic committed Mar 7, 2019
1 parent 16d98c2 commit 3d3120d
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Showing 5 changed files with 70 additions and 36 deletions.
15 changes: 14 additions & 1 deletion llvm/lib/Target/Mips/MipsInstructionSelector.cpp
View file
Expand Up @@ -131,10 +131,23 @@ bool MipsInstructionSelector::select(MachineInstr &I,
return true;
}

if (selectImpl(I, CoverageInfo)) {
if (I.getOpcode() == Mips::G_MUL) {
MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
.add(I.getOperand(0))
.add(I.getOperand(1))
.add(I.getOperand(2));
if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
return false;
Mul->getOperand(3).setIsDead(true);
Mul->getOperand(4).setIsDead(true);

I.eraseFromParent();
return true;
}

if (selectImpl(I, CoverageInfo))
return true;

MachineInstr *MI = nullptr;
using namespace TargetOpcode;

Expand Down
30 changes: 18 additions & 12 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
View file
Expand Up @@ -3,7 +3,7 @@
--- |

define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }

...
---
Expand All @@ -20,7 +20,7 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def $hi0, implicit-def $lo0
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
; MIPS32: $v0 = COPY [[MUL]]
; MIPS32: RetRA implicit $v0
%0:gprb(s32) = COPY $a0
Expand All @@ -38,13 +38,15 @@ regBankSelected: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: umul_with_overflow
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
Expand All @@ -54,18 +56,22 @@ body: |
; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
; MIPS32: SB [[AND]], [[COPY2]], 0 :: (store 1 into %ir.pcarry_flag)
; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
; MIPS32: RetRA
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(p0) = COPY $a2
%6:gprb(s32) = G_UMULH %0, %1
%7:gprb(s32) = G_CONSTANT i32 0
%8:gprb(s32) = G_ICMP intpred(ne), %6(s32), %7
%9:gprb(s32) = G_CONSTANT i32 1
%10:gprb(s32) = COPY %8(s32)
%5:gprb(s32) = G_AND %10, %9
G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
%3:gprb(p0) = COPY $a3
%4:gprb(s32) = G_MUL %0, %1
%7:gprb(s32) = G_UMULH %0, %1
%8:gprb(s32) = G_CONSTANT i32 0
%9:gprb(s32) = G_ICMP intpred(ne), %7(s32), %8
%10:gprb(s32) = G_CONSTANT i32 1
%11:gprb(s32) = COPY %9(s32)
%6:gprb(s32) = G_AND %11, %10
G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
RetRA
...
21 changes: 13 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
View file
Expand Up @@ -9,7 +9,7 @@
define void @mul_i16_sext() {entry: ret void}
define void @mul_i16_zext() {entry: ret void}
define void @mul_i16_aext() {entry: ret void}
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }

...
---
Expand Down Expand Up @@ -218,26 +218,31 @@ alignment: 2
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: umul_with_overflow
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into %ir.pmul)
; MIPS32: RetRA
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(s32), %4:_(s1) = G_UMULO %0, %1
G_STORE %4(s1), %2(p0) :: (store 1 into %ir.pcarry_flag)
%3:_(p0) = COPY $a3
%4:_(s32), %5:_(s1) = G_UMULO %0, %1
G_STORE %5(s1), %3(p0) :: (store 1 into %ir.pcarry_flag)
G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
RetRA
...
8 changes: 6 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
View file
Expand Up @@ -88,9 +88,10 @@ entry:
}

declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) {
; MIPS32-LABEL: umul_with_overflow:
; MIPS32: # %bb.0:
; MIPS32-NEXT: mul $1, $4, $5
; MIPS32-NEXT: multu $4, $5
; MIPS32-NEXT: mfhi $4
; MIPS32-NEXT: lui $5, 0
Expand All @@ -100,11 +101,14 @@ define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
; MIPS32-NEXT: lui $5, 0
; MIPS32-NEXT: ori $5, $5, 1
; MIPS32-NEXT: and $4, $4, $5
; MIPS32-NEXT: sb $4, 0($6)
; MIPS32-NEXT: sb $4, 0($7)
; MIPS32-NEXT: sw $1, 0($6)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
%res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
%carry_flag = extractvalue { i32, i1 } %res, 1
%mul = extractvalue { i32, i1 } %res, 0
store i1 %carry_flag, i1* %pcarry_flag
store i32 %mul, i32* %pmul
ret void
}
32 changes: 19 additions & 13 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
View file
Expand Up @@ -3,7 +3,7 @@
--- |

define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }

...
---
Expand Down Expand Up @@ -36,31 +36,37 @@ legalized: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
liveins: $a0, $a1, $a2
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: umul_with_overflow
; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C1]]
; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C1]]
; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into %ir.pmul)
; MIPS32: RetRA
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
%6:_(s32) = G_UMULH %0, %1
%7:_(s32) = G_CONSTANT i32 0
%8:_(s32) = G_ICMP intpred(ne), %6(s32), %7
%9:_(s32) = G_CONSTANT i32 1
%10:_(s32) = COPY %8(s32)
%5:_(s32) = G_AND %10, %9
G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
%3:_(p0) = COPY $a3
%4:_(s32) = G_MUL %0, %1
%7:_(s32) = G_UMULH %0, %1
%8:_(s32) = G_CONSTANT i32 0
%9:_(s32) = G_ICMP intpred(ne), %7(s32), %8
%10:_(s32) = G_CONSTANT i32 1
%11:_(s32) = COPY %9(s32)
%6:_(s32) = G_AND %11, %10
G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
RetRA
...

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