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[MC] Add parameter Address to MCInstrPrinter::printInstruction
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Follow-up of D72172.

Reviewed By: jhenderson, rnk

Differential Revision: https://reviews.llvm.org/D72180
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MaskRay committed Jan 7, 2020
1 parent aa70876 commit 3d87d0b
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Showing 39 changed files with 59 additions and 58 deletions.
Expand Up @@ -296,7 +296,7 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
}

if (!printAliasInstr(MI, STI, O))
printInstruction(MI, STI, O);
printInstruction(MI, Address, STI, O);

printAnnotation(O, Annot);

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8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
Expand Up @@ -30,8 +30,8 @@ class AArch64InstPrinter : public MCInstPrinter {
void printRegName(raw_ostream &OS, unsigned RegNo) const override;

// Autogenerated by tblgen.
virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
virtual void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O);
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
Expand Down Expand Up @@ -200,8 +200,8 @@ class AArch64AppleInstPrinter : public AArch64InstPrinter {
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;

void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O) override;
void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O) override;
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O) override;
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Expand Up @@ -30,7 +30,7 @@ void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
OS.flush();
printInstruction(MI, STI, OS);
printInstruction(MI, Address, STI, OS);
printAnnotation(OS, Annot);
}

Expand Down Expand Up @@ -1347,7 +1347,7 @@ void R600InstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
O.flush();
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);
}

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
Expand Up @@ -23,8 +23,8 @@ class AMDGPUInstPrinter : public MCInstPrinter {
: MCInstPrinter(MAI, MII, MRI) {}

//Autogenerated by tblgen
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
Expand Down Expand Up @@ -242,7 +242,7 @@ class R600InstPrinter : public MCInstPrinter {

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp
Expand Up @@ -100,7 +100,7 @@ void ARCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
void ARCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);
}

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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h
Expand Up @@ -26,7 +26,7 @@ class ARCInstPrinter : public MCInstPrinter {
: MCInstPrinter(MAI, MII, MRI) {}

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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6 changes: 3 additions & 3 deletions llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
Expand Up @@ -276,7 +276,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
// Copy the rest operands into NewMI.
for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
NewMI.addOperand(MI->getOperand(i));
printInstruction(&NewMI, STI, O);
printInstruction(&NewMI, Address, STI, O);
return;
}
break;
Expand All @@ -289,7 +289,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
switch (MI->getOperand(0).getImm()) {
default:
if (!printAliasInstr(MI, STI, O))
printInstruction(MI, STI, O);
printInstruction(MI, Address, STI, O);
break;
case 0:
O << "\tssbb";
Expand All @@ -303,7 +303,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}

if (!printAliasInstr(MI, STI, O))
printInstruction(MI, STI, O);
printInstruction(MI, Address, STI, O);

printAnnotation(O, Annot);
}
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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
Expand Up @@ -30,8 +30,8 @@ class ARMInstPrinter : public MCInstPrinter {
void printRegName(raw_ostream &OS, unsigned RegNo) const override;

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O);
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
Expand Up @@ -79,7 +79,7 @@ void AVRInstPrinter::printInst(const MCInst *MI, uint64_t Address,
break;
default:
if (!printAliasInstr(MI, O))
printInstruction(MI, O);
printInstruction(MI, Address, O);

printAnnotation(O, Annot);
break;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h
Expand Up @@ -41,7 +41,7 @@ class AVRInstPrinter : public MCInstPrinter {
void printMemri(const MCInst *MI, unsigned OpNo, raw_ostream &O);

// Autogenerated by TableGen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
Expand Up @@ -27,7 +27,7 @@ using namespace llvm;
void BPFInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);
}

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2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h
Expand Up @@ -32,7 +32,7 @@ class BPFInstPrinter : public MCInstPrinter {
void printBrTargetOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
};
}
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6 changes: 3 additions & 3 deletions llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
Expand Up @@ -40,12 +40,12 @@ void HexagonInstPrinter::printInst(const MCInst *MI, uint64_t Address,
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MI)) {
MCInst const &MCI = *I.getInst();
if (HexagonMCInstrInfo::isDuplex(MII, MCI)) {
printInstruction(MCI.getOperand(1).getInst(), OS);
printInstruction(MCI.getOperand(1).getInst(), Address, OS);
OS << '\v';
HasExtender = false;
printInstruction(MCI.getOperand(0).getInst(), OS);
printInstruction(MCI.getOperand(0).getInst(), Address, OS);
} else
printInstruction(&MCI, OS);
printInstruction(&MCI, Address, OS);
HasExtender = HexagonMCInstrInfo::isImmext(MCI);
OS << "\n";
}
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
Expand Up @@ -34,7 +34,7 @@ class HexagonInstPrinter : public MCInstPrinter {

static char const *getRegisterName(unsigned RegNo);

void printInstruction(MCInst const *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
void printOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;
void printBrtarget(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;

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2 changes: 1 addition & 1 deletion llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp
Expand Up @@ -142,7 +142,7 @@ void LanaiInstPrinter::printInst(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo & /*STI*/,
raw_ostream &OS) {
if (!printAlias(MI, OS) && !printAliasInstr(MI, OS))
printInstruction(MI, OS);
printInstruction(MI, Address, OS);
printAnnotation(OS, Annotation);
}

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2 changes: 1 addition & 1 deletion llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h
Expand Up @@ -43,7 +43,7 @@ class LanaiInstPrinter : public MCInstPrinter {
void printMemImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp
Expand Up @@ -30,7 +30,7 @@ void MSP430InstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
if (!printAliasInstr(MI, O))
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h
Expand Up @@ -26,7 +26,7 @@ namespace llvm {
const MCSubtargetInfo &STI, raw_ostream &O) override;

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
Expand Up @@ -110,7 +110,7 @@ void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,

// Try to print any aliases first.
if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);

switch (MI->getOpcode()) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
Expand Up @@ -79,7 +79,7 @@ class MipsInstPrinter : public MCInstPrinter {
: MCInstPrinter(MAI, MII, MRI) {}

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

void printRegName(raw_ostream &OS, unsigned RegNo) const override;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
Expand Up @@ -75,7 +75,7 @@ void NVPTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
void NVPTXInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
printInstruction(MI, OS);
printInstruction(MI, Address, OS);

// Next always print the annotation.
printAnnotation(OS, Annot);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
Expand Up @@ -29,7 +29,7 @@ class NVPTXInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &OS) override;

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
// End

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
Expand Up @@ -194,7 +194,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}

if (!printAliasInstr(MI, O))
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
Expand Up @@ -36,7 +36,7 @@ class PPCInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O) override;

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
Expand Up @@ -74,7 +74,7 @@ void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
if (Res)
NewMI = const_cast<MCInst *>(&UncompressedMI);
if (NoAliases || !printAliasInstr(NewMI, STI, O))
printInstruction(NewMI, STI, O);
printInstruction(NewMI, Address, STI, O);
printAnnotation(O, Annot);
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
Expand Up @@ -43,8 +43,8 @@ class RISCVInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
Expand Up @@ -47,7 +47,7 @@ void SparcInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O))
printInstruction(MI, STI, O);
printInstruction(MI, Address, STI, O);
printAnnotation(O, Annot);
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h
Expand Up @@ -31,8 +31,8 @@ class SparcInstPrinter : public MCInstPrinter {
bool isV9(const MCSubtargetInfo &STI) const;

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
Expand Down
Expand Up @@ -58,7 +58,7 @@ void SystemZInstPrinter::printOperand(const MCOperand &MO, const MCAsmInfo *MAI,
void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h
Expand Up @@ -27,7 +27,7 @@ class SystemZInstPrinter : public MCInstPrinter {
: MCInstPrinter(MAI, MII, MRI) {}

// Automatically generated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

// Print an address with the given base, displacement and index.
Expand Down
Expand Up @@ -49,7 +49,7 @@ void WebAssemblyInstPrinter::printInst(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI,
raw_ostream &OS) {
// Print the instruction (this uses the AsmStrings from the .td files).
printInstruction(MI, OS);
printInstruction(MI, Address, OS);

// Print any additional variadic operands.
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
Expand Down
Expand Up @@ -49,7 +49,7 @@ class WebAssemblyInstPrinter final : public MCInstPrinter {
raw_ostream &O);

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
};

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
Expand Up @@ -70,7 +70,7 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
// Try to print any aliases first.
else if (!printAliasInstr(MI, OS) &&
!printVecCompareInstr(MI, OS))
printInstruction(MI, OS);
printInstruction(MI, Address, OS);

// Next always print the annotation.
printAnnotation(OS, Annot);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
Expand Up @@ -35,7 +35,7 @@ class X86ATTInstPrinter final : public X86InstPrinterCommon {
unsigned PrintMethodIdx, raw_ostream &O);

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &OS);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &OS);
static const char *getRegisterName(unsigned RegNo);

void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
Expand Up @@ -47,7 +47,7 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
OS << "\tdata32";
} else if (!printAliasInstr(MI, OS) &&
!printVecCompareInstr(MI, OS))
printInstruction(MI, OS);
printInstruction(MI, Address, OS);

// Next always print the annotation.
printAnnotation(OS, Annot);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h
Expand Up @@ -36,7 +36,7 @@ class X86IntelInstPrinter final : public X86InstPrinterCommon {
unsigned PrintMethodIdx, raw_ostream &O);

// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);

void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp
Expand Up @@ -33,7 +33,7 @@ void XCoreInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
void XCoreInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &O) {
printInstruction(MI, O);
printInstruction(MI, Address, O);
printAnnotation(O, Annot);
}

Expand Down

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