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[mips] Improve robustness of some tests.

Summary:
This is done by removing some hardcoded registers like $at or expecting a single digit register to be selected.

Contains work done by Matheus Almeida.

Reviewers: matheusalmeida, dsanders

Reviewed By: dsanders

Subscribers: tomatabacu

Differential Revision: http://reviews.llvm.org/D4227

llvm-svn: 223012
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@dsandersllvm
dsandersllvm committed Dec 1, 2014
1 parent 7863d07 commit 3f173e8
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Showing 7 changed files with 65 additions and 65 deletions.
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/cconv/arguments-float.ll
View file
Expand Up @@ -69,26 +69,26 @@ entry:
; O32-DAG: sw [[R4]], 28([[R2]])
; NEW-DAG: sd $6, 24([[R2]])

; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 36($sp)
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
; O32-DAG: sw [[R3]], 32([[R2]])
; O32-DAG: sw [[R4]], 36([[R2]])
; NEW-DAG: sd $7, 32([[R2]])

; O32-DAG: lw [[R3:\$[0-9]+]], 40($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 44($sp)
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
; O32-DAG: sw [[R3]], 40([[R2]])
; O32-DAG: sw [[R4]], 44([[R2]])
; NEW-DAG: sd $8, 40([[R2]])

; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 52($sp)
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)
; O32-DAG: sw [[R3]], 48([[R2]])
; O32-DAG: sw [[R4]], 52([[R2]])
; NEW-DAG: sd $9, 48([[R2]])

; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp)
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 56($sp)
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 60($sp)
; O32-DAG: sw [[R3]], 56([[R2]])
; O32-DAG: sw [[R4]], 60([[R2]])
; NEW-DAG: sd $10, 56([[R2]])
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/cconv/arguments.ll
View file
Expand Up @@ -53,7 +53,7 @@ entry:
; We won't test the way the global address is calculated in this test. This is
; just to get the register number for the other checks.
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)(
; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(

; The first four arguments are the same in O32/N32/N64
; ALL-DAG: sb $4, 1([[R1]])
Expand Down Expand Up @@ -117,9 +117,9 @@ entry:
; We won't test the way the global address is calculated in this test. This is
; just to get the register number for the other checks.
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)(
; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(dwords)(
; SYM64-DAG: ld [[R2:\$[0-9]+]], %got_disp(dwords)(

; The first argument is the same in O32/N32/N64.
; ALL-DAG: sb $4, 1([[R1]])
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/cconv/return-float.ll
View file
Expand Up @@ -30,7 +30,7 @@ entry:
; O32-DAG: lw $2, %lo(float)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
; N32-DAG: lw $2, %lo(float)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1)
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)(
; N64-DAG: lw $2, 0([[R1]])

define double @retdouble() nounwind {
Expand All @@ -44,5 +44,5 @@ entry:
; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(double)
; O32-DAG: lw $3, 4([[R2]])
; N32-DAG: ld $2, %lo(double)([[R1:\$[0-9]+]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1)
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)(
; N64-DAG: ld $2, 0([[R1]])
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/cconv/return-hard-float.ll
View file
Expand Up @@ -33,7 +33,7 @@ entry:
; O32-DAG: lwc1 $f0, %lo(float)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
; N32-DAG: lwc1 $f0, %lo(float)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1)
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)(
; N64-DAG: lwc1 $f0, 0([[R1]])

define double @retdouble() nounwind {
Expand All @@ -45,7 +45,7 @@ entry:
; ALL-LABEL: retdouble:
; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1)
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)(
; N64-DAG: ldc1 $f0, 0([[R1]])

define { double, double } @retComplexDouble() #0 {
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/cconv/return.ll
View file
Expand Up @@ -33,7 +33,7 @@ entry:
; O32-DAG: lbu $2, %lo(byte)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(byte)
; N32-DAG: lbu $2, %lo(byte)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)($1)
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)(
; N64-DAG: lbu $2, 0([[R1]])

define i32 @reti32() nounwind {
Expand All @@ -47,7 +47,7 @@ entry:
; O32-DAG: lw $2, %lo(word)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(word)
; N32-DAG: lw $2, %lo(word)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)($1)
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)(
; N64-DAG: lw $2, 0([[R1]])

define i64 @reti64() nounwind {
Expand Down
92 changes: 46 additions & 46 deletions llvm/test/CodeGen/Mips/msa/frameindex.ll
View file
Expand Up @@ -36,10 +36,10 @@ define void @loadstore_v16i8_just_over_simm10() nounwind {
%2 = alloca [497 x i8] ; Push the frame just over 512 bytes

%3 = load volatile <16 x i8>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
; MIPS32-AE: st.b [[R1]], 0([[BASE]])

ret void
Expand All @@ -53,12 +53,12 @@ define void @loadstore_v16i8_just_under_simm16() nounwind {
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes

%3 = load volatile <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.b [[R1]], 0([[BASE]])

ret void
Expand All @@ -72,12 +72,12 @@ define void @loadstore_v16i8_just_over_simm16() nounwind {
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes

%3 = load volatile <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.b [[R1]], 0([[BASE]])

ret void
Expand Down Expand Up @@ -107,10 +107,10 @@ define void @loadstore_v8i16_unaligned() nounwind {
%5 = getelementptr [2 x <8 x i16>]* %4, i32 0, i32 0

%6 = load volatile <8 x i16>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %6, <8 x i16>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: st.h [[R1]], 0([[BASE]])

ret void
Expand Down Expand Up @@ -139,10 +139,10 @@ define void @loadstore_v8i16_just_over_simm10() nounwind {
%2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes

%3 = load volatile <8 x i16>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
; MIPS32-AE: st.h [[R1]], 0([[BASE]])

ret void
Expand All @@ -156,12 +156,12 @@ define void @loadstore_v8i16_just_under_simm16() nounwind {
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes

%3 = load volatile <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.h [[R1]], 0([[BASE]])

ret void
Expand All @@ -175,12 +175,12 @@ define void @loadstore_v8i16_just_over_simm16() nounwind {
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes

%3 = load volatile <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.h [[R1]], 0([[BASE]])

ret void
Expand Down Expand Up @@ -210,10 +210,10 @@ define void @loadstore_v4i32_unaligned() nounwind {
%5 = getelementptr [2 x <4 x i32>]* %4, i32 0, i32 0

%6 = load volatile <4 x i32>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %6, <4 x i32>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: st.w [[R1]], 0([[BASE]])

ret void
Expand Down Expand Up @@ -242,10 +242,10 @@ define void @loadstore_v4i32_just_over_simm10() nounwind {
%2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes

%3 = load volatile <4 x i32>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
; MIPS32-AE: st.w [[R1]], 0([[BASE]])

ret void
Expand All @@ -259,12 +259,12 @@ define void @loadstore_v4i32_just_under_simm16() nounwind {
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes

%3 = load volatile <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.w [[R1]], 0([[BASE]])

ret void
Expand All @@ -278,12 +278,12 @@ define void @loadstore_v4i32_just_over_simm16() nounwind {
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes

%3 = load volatile <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.w [[R1]], 0([[BASE]])

ret void
Expand Down Expand Up @@ -313,10 +313,10 @@ define void @loadstore_v2i64_unaligned() nounwind {
%5 = getelementptr [2 x <2 x i64>]* %4, i32 0, i32 0

%6 = load volatile <2 x i64>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %6, <2 x i64>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: st.d [[R1]], 0([[BASE]])

ret void
Expand Down Expand Up @@ -345,10 +345,10 @@ define void @loadstore_v2i64_just_over_simm10() nounwind {
%2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes

%3 = load volatile <2 x i64>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
; MIPS32-AE: st.d [[R1]], 0([[BASE]])

ret void
Expand All @@ -362,12 +362,12 @@ define void @loadstore_v2i64_just_under_simm16() nounwind {
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes

%3 = load volatile <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.d [[R1]], 0([[BASE]])

ret void
Expand All @@ -381,12 +381,12 @@ define void @loadstore_v2i64_just_over_simm16() nounwind {
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes

%3 = load volatile <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.d [[R1]], 0([[BASE]])

ret void
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/octeon_popcnt.ll
View file
Expand Up @@ -6,7 +6,7 @@ define i8 @cnt8(i8 %x) nounwind readnone {
ret i8 %cnt
; OCTEON-LABEL: cnt8:
; OCTEON: jr $ra
; OCTEON: pop $2, $1
; OCTEON: pop $2, [[R1:\$[0-9]+]]
; MIPS64-LABEL: cnt8:
; MIPS64-NOT: pop
}
Expand All @@ -16,7 +16,7 @@ define i16 @cnt16(i16 %x) nounwind readnone {
ret i16 %cnt
; OCTEON-LABEL: cnt16:
; OCTEON: jr $ra
; OCTEON: pop $2, $1
; OCTEON: pop $2, [[R1:\$[0-9]+]]
; MIPS64-LABEL: cnt16:
; MIPS64-NOT: pop
}
Expand Down

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