[DPWBS-1361] Adding Instruction Selection support for G_CTLZ and the …

…corresponding test case.

llvm/lib/Target/TriCore/TriCoreGISelPattern.td

@@ -113,6 +113,10 @@ def : SimpleBinOpPat<and, AND_ddd>;
 def : SimpleBinOpPat<or,  OR_ddd>;
 def : SimpleBinOpPat<xor, XOR_ddd>;
 
+// 2.1.9 Count Leading Zeros, Ones and Signs
+
+def : Pat<(i32 (ctlz i32:$src)), (i32 (CLZ_dd DataRegs:$src))>;
+
 // 2.1.10 Shift.
 
 def : SimpleBinOpPat<shl, SH_ddd>;

llvm/test/CodeGen/TriCore/GlobalIsel/select-ctlz.mir

@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=tricore -global-isel -run-pass=instruction-select \
+# RUN:    -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            test_ctlz_s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: dataregbank }
+  - { id: 1, class: dataregbank }
+
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_ctlz_s32
+    ; CHECK: [[COPY:%[0-9]+]]:dataregs = COPY $d4
+    ; CHECK: [[CLZ_dd:%[0-9]+]]:dataregs = CLZ_dd [[COPY]]
+    ; CHECK: $d4 = COPY [[CLZ_dd]]
+    %0(s32) = COPY $d4
+    %1(s32) = G_CTLZ %0
+    $d4 = COPY %1(s32)
+...