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[AMDGPU][True16] Pre-commit addition tests.
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Differential Revision: https://reviews.llvm.org/D156529
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@kosarev
kosarev committed Sep 27, 2023
1 parent 0c77171 commit 3ff7d51
Showing 1 changed file with 122 additions and 0 deletions.
122 changes: 122 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fadd.f16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=VI %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11 %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s

define amdgpu_kernel void @fadd_f16(
; SI-LABEL: fadd_f16:
Expand Down Expand Up @@ -78,6 +79,32 @@ define amdgpu_kernel void @fadd_f16(
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fadd_f16:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
; GFX11-FAKE16-NEXT: s_mov_b32 s11, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s10, -1
; GFX11-FAKE16-NEXT: s_mov_b32 s3, s11
; GFX11-FAKE16-NEXT: s_mov_b32 s2, s10
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s4
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s5
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7
; GFX11-FAKE16-NEXT: s_mov_b32 s6, s10
; GFX11-FAKE16-NEXT: s_mov_b32 s7, s11
; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0 glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: buffer_load_u16 v1, off, s[0:3], 0 glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0
; GFX11-FAKE16-NEXT: s_nop 0
; GFX11-FAKE16-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
Expand Down Expand Up @@ -147,6 +174,26 @@ define amdgpu_kernel void @fadd_f16_imm_a(
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fadd_f16_imm_a:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
; GFX11-FAKE16-NEXT: s_mov_b32 s2, s6
; GFX11-FAKE16-NEXT: s_mov_b32 s3, s7
; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[0:3], 0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_nop 0
; GFX11-FAKE16-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %b) {
entry:
Expand Down Expand Up @@ -214,6 +261,26 @@ define amdgpu_kernel void @fadd_f16_imm_b(
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fadd_f16_imm_b:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
; GFX11-FAKE16-NEXT: s_mov_b32 s2, s6
; GFX11-FAKE16-NEXT: s_mov_b32 s3, s7
; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[0:3], 0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 2.0, v0
; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_nop 0
; GFX11-FAKE16-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
Expand Down Expand Up @@ -303,6 +370,27 @@ define amdgpu_kernel void @fadd_v2f16(
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fadd_v2f16:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
; GFX11-FAKE16-NEXT: s_load_b64 s[8:9], s[0:1], 0x34
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: global_load_b32 v1, v0, s[6:7]
; GFX11-FAKE16-NEXT: global_load_b32 v0, v0, s[8:9]
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s4
; GFX11-FAKE16-NEXT: s_mov_b32 s1, s5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, v1, v0
; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-FAKE16-NEXT: s_nop 0
; GFX11-FAKE16-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a,
ptr addrspace(1) %b) {
Expand Down Expand Up @@ -382,6 +470,23 @@ define amdgpu_kernel void @fadd_v2f16_imm_a(
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fadd_v2f16_imm_a:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b32 v0, v0, s[2:3]
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x40003c00, v0
; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_nop 0
; GFX11-FAKE16-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %b) {
entry:
Expand Down Expand Up @@ -458,6 +563,23 @@ define amdgpu_kernel void @fadd_v2f16_imm_b(
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fadd_v2f16_imm_b:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b32 v0, v0, s[2:3]
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x3c004000, v0
; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_nop 0
; GFX11-FAKE16-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
Expand Down

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