[RISCV] Obey -riscv-v-fixed-length-vector-elen-max when lowering mask…

… BUILD_VECTORs. We may not be allowed to use vXiXLen vectors. Consult ELEN to determine what is allowed. This will become even more important when Zve32 is added. Reviewed By: frasercrmck, arcbbb Differential Revision: https://reviews.llvm.org/D117518
llvm · Jan 19, 2022 · 4060b81 · 4060b81
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commit 4060b81
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1929,6 +1929,8 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
     // codegen across RV32 and RV64.
     unsigned NumViaIntegerBits =
         std::min(std::max(NumElts, 8u), Subtarget.getXLen());
+    NumViaIntegerBits = std::min(NumViaIntegerBits,
+                                 Subtarget.getMaxELENForFixedLengthVectors());
     if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
       // If we have to use more than one INSERT_VECTOR_ELT then this
       // optimization is likely to increase code size; avoid peforming it in