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[PowerPC][NFC] Update builtins-ppc-xlcompat-trap-64bit-only.ll and bu…
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…iltins-ppc-xlcompat-trap.ll to show full reg names
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@VictorHuangIBM
VictorHuangIBM committed Oct 28, 2021
1 parent 2b1e324 commit 40cad47
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Showing 2 changed files with 35 additions and 35 deletions.
34 changes: 17 additions & 17 deletions llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
View file
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s
; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
; RUN: -mcpu=pwr8 < %s | FileCheck %s
; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s

; tdw
declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlgt:
; CHECK: # %bb.0:
; CHECK-NEXT: tdlgt 3, 4
; CHECK-NEXT: tdlgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
ret void
Expand All @@ -20,7 +20,7 @@ define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
define dso_local void @test__tdwllt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwllt:
; CHECK: # %bb.0:
; CHECK-NEXT: tdllt 3, 4
; CHECK-NEXT: tdllt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
ret void
Expand All @@ -29,15 +29,15 @@ define dso_local void @test__tdwllt(i64 %a, i64 %b) {
define dso_local void @test__tdw3(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdw3:
; CHECK: # %bb.0:
; CHECK-NEXT: td 3, 3, 4
; CHECK-NEXT: td 3, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 3)
ret void
}
define dso_local void @test__tdweq(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdweq:
; CHECK: # %bb.0:
; CHECK-NEXT: tdeq 3, 4
; CHECK-NEXT: tdeq r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
ret void
Expand All @@ -46,7 +46,7 @@ define dso_local void @test__tdweq(i64 %a, i64 %b) {
define dso_local void @test__tdwlge(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlge:
; CHECK: # %bb.0:
; CHECK-NEXT: td 5, 3, 4
; CHECK-NEXT: td 5, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
ret void
Expand All @@ -55,7 +55,7 @@ define dso_local void @test__tdwlge(i64 %a, i64 %b) {
define dso_local void @test__tdwlle(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlle:
; CHECK: # %bb.0:
; CHECK-NEXT: td 6, 3, 4
; CHECK-NEXT: td 6, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
ret void
Expand All @@ -64,7 +64,7 @@ define dso_local void @test__tdwlle(i64 %a, i64 %b) {
define dso_local void @test__tdwgt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwgt:
; CHECK: # %bb.0:
; CHECK-NEXT: tdgt 3, 4
; CHECK-NEXT: tdgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
ret void
Expand All @@ -73,7 +73,7 @@ define dso_local void @test__tdwgt(i64 %a, i64 %b) {
define dso_local void @test__tdwge(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwge:
; CHECK: # %bb.0:
; CHECK-NEXT: td 12, 3, 4
; CHECK-NEXT: td 12, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
ret void
Expand All @@ -82,7 +82,7 @@ define dso_local void @test__tdwge(i64 %a, i64 %b) {
define dso_local void @test__tdwlt(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwlt:
; CHECK: # %bb.0:
; CHECK-NEXT: tdlt 3, 4
; CHECK-NEXT: tdlt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
ret void
Expand All @@ -91,7 +91,7 @@ define dso_local void @test__tdwlt(i64 %a, i64 %b) {
define dso_local void @test__tdwle(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwle:
; CHECK: # %bb.0:
; CHECK-NEXT: td 20, 3, 4
; CHECK-NEXT: td 20, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
ret void
Expand All @@ -100,7 +100,7 @@ define dso_local void @test__tdwle(i64 %a, i64 %b) {
define dso_local void @test__tdwne24(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdwne24:
; CHECK: # %bb.0:
; CHECK-NEXT: tdne 3, 4
; CHECK-NEXT: tdne r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
ret void
Expand All @@ -109,7 +109,7 @@ define dso_local void @test__tdwne24(i64 %a, i64 %b) {
define dso_local void @test__tdw31(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdw31:
; CHECK: # %bb.0:
; CHECK-NEXT: tdu 3, 4
; CHECK-NEXT: tdu r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
ret void
Expand All @@ -118,7 +118,7 @@ define dso_local void @test__tdw31(i64 %a, i64 %b) {
define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
; CHECK-LABEL: test__tdw_no_match:
; CHECK: # %bb.0:
; CHECK-NEXT: td 13, 3, 4
; CHECK-NEXT: td 13, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
ret void
Expand All @@ -129,7 +129,7 @@ declare void @llvm.ppc.trapd(i64 %a)
define dso_local void @test__trapd(i64 %a) {
; CHECK-LABEL: test__trapd:
; CHECK: # %bb.0:
; CHECK-NEXT: tdnei 3, 0
; CHECK-NEXT: tdnei r3, 0
; CHECK-NEXT: blr
call void @llvm.ppc.trapd(i64 %a)
ret void
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
View file
@@ -1,19 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s
; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
; RUN: -mcpu=pwr8 < %s | FileCheck %s
; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
; RUN: -mcpu=pwr8 < %s | FileCheck %s
; RUN: --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s

; tw
declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
define dso_local void @test__twlgt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlgt:
; CHECK: # %bb.0:
; CHECK-NEXT: twlgt 3, 4
; CHECK-NEXT: twlgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
ret void
Expand All @@ -22,7 +22,7 @@ define dso_local void @test__twlgt(i32 %a, i32 %b) {
define dso_local void @test__twllt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twllt:
; CHECK: # %bb.0:
; CHECK-NEXT: twllt 3, 4
; CHECK-NEXT: twllt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
ret void
Expand All @@ -31,7 +31,7 @@ define dso_local void @test__twllt(i32 %a, i32 %b) {
define dso_local void @test__tw3(i32 %a, i32 %b) {
; CHECK-LABEL: test__tw3:
; CHECK: # %bb.0:
; CHECK-NEXT: tw 3, 3, 4
; CHECK-NEXT: tw 3, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
ret void
Expand All @@ -40,7 +40,7 @@ define dso_local void @test__tw3(i32 %a, i32 %b) {
define dso_local void @test__tweq(i32 %a, i32 %b) {
; CHECK-LABEL: test__tweq:
; CHECK: # %bb.0:
; CHECK-NEXT: tweq 3, 4
; CHECK-NEXT: tweq r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
ret void
Expand All @@ -49,7 +49,7 @@ define dso_local void @test__tweq(i32 %a, i32 %b) {
define dso_local void @test__twlge(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlge:
; CHECK: # %bb.0:
; CHECK-NEXT: tw 5, 3, 4
; CHECK-NEXT: tw 5, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
ret void
Expand All @@ -58,7 +58,7 @@ define dso_local void @test__twlge(i32 %a, i32 %b) {
define dso_local void @test__twlle(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlle:
; CHECK: # %bb.0:
; CHECK-NEXT: tw 6, 3, 4
; CHECK-NEXT: tw 6, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
ret void
Expand All @@ -67,7 +67,7 @@ define dso_local void @test__twlle(i32 %a, i32 %b) {
define dso_local void @test__twgt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twgt:
; CHECK: # %bb.0:
; CHECK-NEXT: twgt 3, 4
; CHECK-NEXT: twgt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
ret void
Expand All @@ -76,7 +76,7 @@ define dso_local void @test__twgt(i32 %a, i32 %b) {
define dso_local void @test__twge(i32 %a, i32 %b) {
; CHECK-LABEL: test__twge:
; CHECK: # %bb.0:
; CHECK-NEXT: tw 12, 3, 4
; CHECK-NEXT: tw 12, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
ret void
Expand All @@ -85,7 +85,7 @@ define dso_local void @test__twge(i32 %a, i32 %b) {
define dso_local void @test__twlt(i32 %a, i32 %b) {
; CHECK-LABEL: test__twlt:
; CHECK: # %bb.0:
; CHECK-NEXT: twlt 3, 4
; CHECK-NEXT: twlt r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
ret void
Expand All @@ -94,7 +94,7 @@ define dso_local void @test__twlt(i32 %a, i32 %b) {
define dso_local void @test__twle(i32 %a, i32 %b) {
; CHECK-LABEL: test__twle:
; CHECK: # %bb.0:
; CHECK-NEXT: tw 20, 3, 4
; CHECK-NEXT: tw 20, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
ret void
Expand All @@ -103,7 +103,7 @@ define dso_local void @test__twle(i32 %a, i32 %b) {
define dso_local void @test__twne24(i32 %a, i32 %b) {
; CHECK-LABEL: test__twne24:
; CHECK: # %bb.0:
; CHECK-NEXT: twne 3, 4
; CHECK-NEXT: twne r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
ret void
Expand All @@ -112,7 +112,7 @@ define dso_local void @test__twne24(i32 %a, i32 %b) {
define dso_local void @test__twu(i32 %a, i32 %b) {
; CHECK-LABEL: test__twu:
; CHECK: # %bb.0:
; CHECK-NEXT: twu 3, 4
; CHECK-NEXT: twu r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
ret void
Expand All @@ -121,7 +121,7 @@ define dso_local void @test__twu(i32 %a, i32 %b) {
define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
; CHECK-LABEL: test__tw_no_match:
; CHECK: # %bb.0:
; CHECK-NEXT: tw 13, 3, 4
; CHECK-NEXT: tw 13, r3, r4
; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
ret void
Expand All @@ -132,7 +132,7 @@ declare void @llvm.ppc.trap(i32 %a)
define dso_local void @test__trap(i32 %a) {
; CHECK-LABEL: test__trap:
; CHECK: # %bb.0:
; CHECK-NEXT: twnei 3, 0
; CHECK-NEXT: twnei r3, 0
; CHECK-NEXT: blr
call void @llvm.ppc.trap(i32 %a)
ret void
Expand Down

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