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[clang-format] Recognize Verilog type dimension in module header
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We had the function `verilogGroupDecl` for that.  However, the type
name would be incorrectly annotated in `isStartOfName` when it was not
a C++ keyword and followed another identifier.

Reviewed By: HazardyKnusperkeks, owenpan, MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D149352
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eywdck2l committed Apr 30, 2023
1 parent 82a90ca commit 4134f83
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Showing 3 changed files with 17 additions and 0 deletions.
4 changes: 4 additions & 0 deletions clang/lib/Format/TokenAnnotator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2165,6 +2165,10 @@ class AnnotatingParser {
/// This is a heuristic based on whether \p Tok is an identifier following
/// something that is likely a type.
bool isStartOfName(const FormatToken &Tok) {
// Handled in ExpressionParser for Verilog.
if (Style.isVerilog())
return false;

if (Tok.isNot(tok::identifier) || !Tok.Previous)
return false;

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6 changes: 6 additions & 0 deletions clang/unittests/Format/FormatTestVerilog.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -359,6 +359,12 @@ TEST_F(FormatTestVerilog, Headers) {
" input var shortreal in2,\n"
" output tagged_st out);\n"
"endmodule");
// There should be a space following the type but not the variable name.
verifyFormat("module test\n"
" (input wire [7 : 0] a,\n"
" input wire b[7 : 0],\n"
" input wire [7 : 0] c[7 : 0]);\n"
"endmodule");
// Ports should be grouped by types.
verifyFormat("module test\n"
" (input [7 : 0] a,\n"
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7 changes: 7 additions & 0 deletions clang/unittests/Format/TokenAnnotatorTest.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1615,6 +1615,13 @@ TEST_F(TokenAnnotatorTest, UnderstandsVerilogOperators) {
Tokens = Annotate("extern function [1 : 0] x;");
ASSERT_EQ(Tokens.size(), 10u) << Tokens;
EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon);
Tokens = Annotate("module test\n"
" (input wire [7 : 0] a[7 : 0]);\n"
"endmodule");
ASSERT_EQ(Tokens.size(), 20u) << Tokens;
EXPECT_TOKEN(Tokens[4], tok::identifier, TT_VerilogDimensionedTypeName);
EXPECT_TOKEN(Tokens[7], tok::colon, TT_BitFieldColon);
EXPECT_TOKEN(Tokens[13], tok::colon, TT_BitFieldColon);
// Test case labels and ternary operators.
Tokens = Annotate("case (x)\n"
" x:\n"
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