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[clang-format] Recognize Verilog type dimension in module header
We had the function `verilogGroupDecl` for that. However, the type name would be incorrectly annotated in `isStartOfName` when it was not a C++ keyword and followed another identifier. Reviewed By: HazardyKnusperkeks, owenpan, MyDeveloperDay Differential Revision: https://reviews.llvm.org/D149352
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