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[RISCV][1/3] Switch undef -> poison in VP RVV tests
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Inspired by a recent Discourse post on undef vs. poison usage, this
series of patches should reduce the number of undefs in LLVM tests by
around 10%.

Only undef vector operands to insertelement/shufflevector have been
handled, which are by far the most common we've got.

The switchover is split into 3 fairly arbitrary clusters to make it
slightly more manageable: vector predication, fixed-length vectors,
scalable vectors.
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@frasercrmck
frasercrmck committed Feb 1, 2022
1 parent a0ea733 commit 414f21e
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Showing 48 changed files with 7,756 additions and 7,756 deletions.
520 changes: 260 additions & 260 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
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488 changes: 244 additions & 244 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
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256 changes: 128 additions & 128 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
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256 changes: 128 additions & 128 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
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204 changes: 102 additions & 102 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
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192 changes: 96 additions & 96 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
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192 changes: 96 additions & 96 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
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144 changes: 72 additions & 72 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
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144 changes: 72 additions & 72 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
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192 changes: 96 additions & 96 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
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276 changes: 138 additions & 138 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
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480 changes: 240 additions & 240 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
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32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
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Expand Up @@ -184,8 +184,8 @@ define <3 x i8> @vpgather_truemask_v3i8(<3 x i8*> %ptrs, i32 zeroext %evl) {
; RV64-NEXT: vluxei64.v v10, (zero), v8
; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <3 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <3 x i1> %mhead, <3 x i1> undef, <3 x i32> zeroinitializer
%mhead = insertelement <3 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <3 x i1> %mhead, <3 x i1> poison, <3 x i32> zeroinitializer
%v = call <3 x i8> @llvm.vp.gather.v3i8.v3p0i8(<3 x i8*> %ptrs, <3 x i1> %mtrue, i32 %evl)
ret <3 x i8> %v
}
Expand Down Expand Up @@ -224,8 +224,8 @@ define <4 x i8> @vpgather_truemask_v4i8(<4 x i8*> %ptrs, i32 zeroext %evl) {
; RV64-NEXT: vluxei64.v v10, (zero), v8
; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i8> @llvm.vp.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret <4 x i8> %v
}
Expand Down Expand Up @@ -457,8 +457,8 @@ define <4 x i16> @vpgather_truemask_v4i16(<4 x i16*> %ptrs, i32 zeroext %evl) {
; RV64-NEXT: vluxei64.v v10, (zero), v8
; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i16> @llvm.vp.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret <4 x i16> %v
}
Expand Down Expand Up @@ -670,8 +670,8 @@ define <4 x i32> @vpgather_truemask_v4i32(<4 x i32*> %ptrs, i32 zeroext %evl) {
; RV64-NEXT: vluxei64.v v10, (zero), v8
; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret <4 x i32> %v
}
Expand Down Expand Up @@ -910,8 +910,8 @@ define <4 x i64> @vpgather_truemask_v4i64(<4 x i64*> %ptrs, i32 zeroext %evl) {
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; RV64-NEXT: vluxei64.v v8, (zero), v8
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.gather.v4i64.v4p0i64(<4 x i64*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret <4 x i64> %v
}
Expand Down Expand Up @@ -1236,8 +1236,8 @@ define <4 x half> @vpgather_truemask_v4f16(<4 x half*> %ptrs, i32 zeroext %evl)
; RV64-NEXT: vluxei64.v v10, (zero), v8
; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x half> @llvm.vp.gather.v4f16.v4p0f16(<4 x half*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret <4 x half> %v
}
Expand Down Expand Up @@ -1407,8 +1407,8 @@ define <4 x float> @vpgather_truemask_v4f32(<4 x float*> %ptrs, i32 zeroext %evl
; RV64-NEXT: vluxei64.v v10, (zero), v8
; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x float> @llvm.vp.gather.v4f32.v4p0f32(<4 x float*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret <4 x float> %v
}
Expand Down Expand Up @@ -1647,8 +1647,8 @@ define <4 x double> @vpgather_truemask_v4f64(<4 x double*> %ptrs, i32 zeroext %e
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; RV64-NEXT: vluxei64.v v8, (zero), v8
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x double> @llvm.vp.gather.v4f64.v4p0f64(<4 x double*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret <4 x double> %v
}
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
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Expand Up @@ -46,7 +46,7 @@ define <4 x i8> @vpload_v4i8_allones_mask(<4 x i8>* %ptr, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i1> undef, i1 true, i32 0
%a = insertelement <4 x i1> poison, i1 true, i32 0
%b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer
%load = call <4 x i8> @llvm.vp.load.v4i8.p0v4i8(<4 x i8>* %ptr, <4 x i1> %b, i32 %evl)
ret <4 x i8> %load
Expand Down Expand Up @@ -106,7 +106,7 @@ define <8 x i16> @vpload_v8i16_allones_mask(<8 x i16>* %ptr, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i1> undef, i1 true, i32 0
%a = insertelement <8 x i1> poison, i1 true, i32 0
%b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer
%load = call <8 x i16> @llvm.vp.load.v8i16.p0v8i16(<8 x i16>* %ptr, <8 x i1> %b, i32 %evl)
ret <8 x i16> %load
Expand Down Expand Up @@ -154,7 +154,7 @@ define <6 x i32> @vpload_v6i32_allones_mask(<6 x i32>* %ptr, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <6 x i1> undef, i1 true, i32 0
%a = insertelement <6 x i1> poison, i1 true, i32 0
%b = shufflevector <6 x i1> %a, <6 x i1> poison, <6 x i32> zeroinitializer
%load = call <6 x i32> @llvm.vp.load.v6i32.p0v6i32(<6 x i32>* %ptr, <6 x i1> %b, i32 %evl)
ret <6 x i32> %load
Expand All @@ -178,7 +178,7 @@ define <8 x i32> @vpload_v8i32_allones_mask(<8 x i32>* %ptr, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i1> undef, i1 true, i32 0
%a = insertelement <8 x i1> poison, i1 true, i32 0
%b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer
%load = call <8 x i32> @llvm.vp.load.v8i32.p0v8i32(<8 x i32>* %ptr, <8 x i1> %b, i32 %evl)
ret <8 x i32> %load
Expand Down Expand Up @@ -214,7 +214,7 @@ define <4 x i64> @vpload_v4i64_allones_mask(<4 x i64>* %ptr, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i1> undef, i1 true, i32 0
%a = insertelement <4 x i1> poison, i1 true, i32 0
%b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer
%load = call <4 x i64> @llvm.vp.load.v4i64.p0v4i64(<4 x i64>* %ptr, <4 x i1> %b, i32 %evl)
ret <4 x i64> %load
Expand Down Expand Up @@ -250,7 +250,7 @@ define <2 x half> @vpload_v2f16_allones_mask(<2 x half>* %ptr, i32 zeroext %evl)
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i1> undef, i1 true, i32 0
%a = insertelement <2 x i1> poison, i1 true, i32 0
%b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer
%load = call <2 x half> @llvm.vp.load.v2f16.p0v2f16(<2 x half>* %ptr, <2 x i1> %b, i32 %evl)
ret <2 x half> %load
Expand Down Expand Up @@ -322,7 +322,7 @@ define <8 x float> @vpload_v8f32_allones_mask(<8 x float>* %ptr, i32 zeroext %ev
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i1> undef, i1 true, i32 0
%a = insertelement <8 x i1> poison, i1 true, i32 0
%b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer
%load = call <8 x float> @llvm.vp.load.v8f32.p0v8f32(<8 x float>* %ptr, <8 x i1> %b, i32 %evl)
ret <8 x float> %load
Expand Down Expand Up @@ -358,7 +358,7 @@ define <4 x double> @vpload_v4f64_allones_mask(<4 x double>* %ptr, i32 zeroext %
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i1> undef, i1 true, i32 0
%a = insertelement <4 x i1> poison, i1 true, i32 0
%b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer
%load = call <4 x double> @llvm.vp.load.v4f64.p0v4f64(<4 x double>* %ptr, <4 x i1> %b, i32 %evl)
ret <4 x double> %load
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
View file
Expand Up @@ -127,8 +127,8 @@ define void @vpscatter_truemask_v4i8(<4 x i8> %val, <4 x i8*> %ptrs, i32 zeroext
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
call void @llvm.vp.scatter.v4i8.v4p0i8(<4 x i8> %val, <4 x i8*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down Expand Up @@ -266,8 +266,8 @@ define void @vpscatter_truemask_v3i16(<3 x i16> %val, <3 x i16*> %ptrs, i32 zero
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <3 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <3 x i1> %mhead, <3 x i1> undef, <3 x i32> zeroinitializer
%mhead = insertelement <3 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <3 x i1> %mhead, <3 x i1> poison, <3 x i32> zeroinitializer
call void @llvm.vp.scatter.v3i16.v3p0i16(<3 x i16> %val, <3 x i16*> %ptrs, <3 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down Expand Up @@ -302,8 +302,8 @@ define void @vpscatter_truemask_v4i16(<4 x i16> %val, <4 x i16*> %ptrs, i32 zero
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
call void @llvm.vp.scatter.v4i16.v4p0i16(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down Expand Up @@ -489,8 +489,8 @@ define void @vpscatter_truemask_v4i32(<4 x i32> %val, <4 x i32*> %ptrs, i32 zero
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
call void @llvm.vp.scatter.v4i32.v4p0i32(<4 x i32> %val, <4 x i32*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down Expand Up @@ -725,8 +725,8 @@ define void @vpscatter_truemask_v4i64(<4 x i64> %val, <4 x i64*> %ptrs, i32 zero
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
call void @llvm.vp.scatter.v4i64.v4p0i64(<4 x i64> %val, <4 x i64*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down Expand Up @@ -1044,8 +1044,8 @@ define void @vpscatter_truemask_v4f16(<4 x half> %val, <4 x half*> %ptrs, i32 ze
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
call void @llvm.vp.scatter.v4f16.v4p0f16(<4 x half> %val, <4 x half*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down Expand Up @@ -1210,8 +1210,8 @@ define void @vpscatter_truemask_v4f32(<4 x float> %val, <4 x float*> %ptrs, i32
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
call void @llvm.vp.scatter.v4f32.v4p0f32(<4 x float> %val, <4 x float*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down Expand Up @@ -1446,8 +1446,8 @@ define void @vpscatter_truemask_v4f64(<4 x double> %val, <4 x double*> %ptrs, i3
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; RV64-NEXT: vsoxei64.v v8, (zero), v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
%mhead = insertelement <4 x i1> poison, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer
call void @llvm.vp.scatter.v4f64.v4p0f64(<4 x double> %val, <4 x double*> %ptrs, <4 x i1> %mtrue, i32 %evl)
ret void
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
View file
Expand Up @@ -274,7 +274,7 @@ define void @vpstore_v2i8_allones_mask(<2 x i8> %val, <2 x i8>* %ptr, i32 zeroex
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i1> undef, i1 true, i32 0
%a = insertelement <2 x i1> poison, i1 true, i32 0
%b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer
call void @llvm.vp.store.v2i8.p0v2i8(<2 x i8> %val, <2 x i8>* %ptr, <2 x i1> %b, i32 %evl)
ret void
Expand Down

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