[LoongArch] Implement isLegalAddImmediate

This brings a trivial improvement in the and-add-lsr.ll test case. Signed-off-by: WANG Rui <wangrui@loongson.cn> Reviewed By: SixWeining, xen0n Differential Revision: https://reviews.llvm.org/D154762
llvm · Jul 24, 2023 · 42dccf9 · 42dccf9
1 parent c100f35
commit 42dccf9
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Showing 3 changed files with 8 additions and 4 deletions.
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -3247,6 +3247,10 @@ bool LoongArchTargetLowering::isLegalAddressingMode(const DataLayout &DL,
   return true;
 }
 
+bool LoongArchTargetLowering::isLegalAddImmediate(int64_t Imm) const {
+  return isInt<12>(Imm);
+}
+
 bool LoongArchTargetLowering::hasAndNotCompare(SDValue Y) const {
   // TODO: Support vectors.
   if (Y.getValueType().isVector())

diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -202,6 +202,8 @@ class LoongArchTargetLowering : public TargetLowering {
                              unsigned AS,
                              Instruction *I = nullptr) const override;
 
+  bool isLegalAddImmediate(int64_t Imm) const override;
+
   bool hasAndNotCompare(SDValue Y) const override;
 
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }

diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
@@ -428,16 +428,14 @@ define i64 @and_i64_0xfff0_multiple_times(i64 %a, i64 %b, i64 %c) {
 define i32 @and_add_lsr(i32 %x, i32 %y) {
 ; LA32-LABEL: and_add_lsr:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a2, $zero, 4095
-; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    addi.w $a0, $a0, -1
 ; LA32-NEXT:    srli.w $a1, $a1, 20
 ; LA32-NEXT:    and $a0, $a1, $a0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: and_add_lsr:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a2, $zero, 4095
-; LA64-NEXT:    add.d $a0, $a0, $a2
+; LA64-NEXT:    addi.d $a0, $a0, -1
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 31, 20
 ; LA64-NEXT:    and $a0, $a1, $a0
 ; LA64-NEXT:    ret