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[SystemZ] Use ISD::ABS opcode during isel.
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The SystemZISD::IABS node is no longer needed since ISD::ABS can be used
instead.

Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D91697
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JonPsson committed Nov 18, 2020
1 parent ccd9091 commit 45b8e37
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Showing 5 changed files with 13 additions and 41 deletions.
6 changes: 4 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Expand Up @@ -164,6 +164,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
++I) {
MVT VT = MVT::SimpleValueType(I);
if (isTypeLegal(VT)) {
setOperationAction(ISD::ABS, VT, Legal);

// Expand individual DIV and REMs into DIVREMs.
setOperationAction(ISD::SDIV, VT, Expand);
setOperationAction(ISD::UDIV, VT, Expand);
Expand Down Expand Up @@ -358,6 +360,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SUB, VT, Legal);
if (VT != MVT::v2i64)
setOperationAction(ISD::MUL, VT, Legal);
setOperationAction(ISD::ABS, VT, Legal);
setOperationAction(ISD::AND, VT, Legal);
setOperationAction(ISD::OR, VT, Legal);
setOperationAction(ISD::XOR, VT, Legal);
Expand Down Expand Up @@ -2960,7 +2963,7 @@ static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
// Return the absolute or negative absolute of Op; IsNegative decides which.
static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
bool IsNegative) {
Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
Op = DAG.getNode(ISD::ABS, DL, Op.getValueType(), Op);
if (IsNegative)
Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
DAG.getConstant(0, DL, Op.getValueType()), Op);
Expand Down Expand Up @@ -5559,7 +5562,6 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
OPCODE(TLS_LDCALL);
OPCODE(PCREL_WRAPPER);
OPCODE(PCREL_OFFSET);
OPCODE(IABS);
OPCODE(ICMP);
OPCODE(FCMP);
OPCODE(STRICT_FCMP);
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.h
Expand Up @@ -50,9 +50,6 @@ enum NodeType : unsigned {
// as a register base.
PCREL_OFFSET,

// Integer absolute.
IABS,

// Integer comparisons. There are three operands: the two values
// to compare, and an integer of type SystemZICMP.
ICMP,
Expand Down
14 changes: 4 additions & 10 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.td
Expand Up @@ -832,16 +832,13 @@ def GOT : Alias<6, (outs GR64:$R1), (ins),

let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>;
def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>;
def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>;
def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>;
}
let CCValues = 0xE, CompareZeroCCMask = 0xE in
def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>;
}
def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>;
def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>;
defm : SXU<z_iabs, LPGFR>;
defm : SXU<z_iabs64, LPGFR>;
defm : SXU<abs, LPGFR>;

let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
Expand All @@ -851,10 +848,7 @@ let Defs = [CC] in {
let CCValues = 0xE, CompareZeroCCMask = 0xE in
def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>;
}
def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>;
def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>;
defm : SXU<z_inegabs, LNGFR>;
defm : SXU<z_inegabs64, LNGFR>;
defm : SXU<z_inegabs, LNGFR>;

let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZInstrVector.td
Expand Up @@ -571,10 +571,10 @@ let Predicates = [FeatureVector] in {

// Load positive.
def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>;
def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>;
def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>;
def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>;
def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>;
def VLPB : UnaryVRRa<"vlpb", 0xE7DF, abs, v128b, v128b, 0>;
def VLPH : UnaryVRRa<"vlph", 0xE7DF, abs, v128h, v128h, 1>;
def VLPF : UnaryVRRa<"vlpf", 0xE7DF, abs, v128f, v128f, 2>;
def VLPG : UnaryVRRa<"vlpg", 0xE7DF, abs, v128g, v128g, 3>;

let isCommutable = 1 in {
// Maximum.
Expand Down
23 changes: 1 addition & 22 deletions llvm/lib/Target/SystemZ/SystemZOperators.td
Expand Up @@ -259,7 +259,6 @@ def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall,
def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET",
SDT_ZWrapOffset, []>;
def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>;
def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp>;
def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp>;
def z_strict_fcmp : SDNode<"SystemZISD::STRICT_FCMP", SDT_ZCmp,
Expand Down Expand Up @@ -667,17 +666,7 @@ def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
}]>;

// Negative integer absolute.
def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;

// Integer absolute, matching the canonical form generated by DAGCombiner.
def z_iabs32 : PatFrag<(ops node:$src),
(xor (add node:$src, (sra node:$src, (i32 31))),
(sra node:$src, (i32 31)))>;
def z_iabs64 : PatFrag<(ops node:$src),
(xor (add node:$src, (sra node:$src, (i32 63))),
(sra node:$src, (i32 63)))>;
def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
def z_inegabs : PatFrag<(ops node:$src), (ineg (abs node:$src))>;

// Integer multiply-and-add
def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
Expand Down Expand Up @@ -894,16 +883,6 @@ def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, immAllZerosV)>;
// Signed "integer less than zero" on vectors.
def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph immAllZerosV, node:$x)>;

// Integer absolute on vectors.
class z_viabs<int shift>
: PatFrag<(ops node:$src),
(xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))),
(z_vsra_by_scalar node:$src, (i32 shift)))>;
def z_viabs8 : z_viabs<7>;
def z_viabs16 : z_viabs<15>;
def z_viabs32 : z_viabs<31>;
def z_viabs64 : z_viabs<63>;

// Sign-extend the i64 elements of a vector.
class z_vse<int shift>
: PatFrag<(ops node:$src),
Expand Down

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