[LoongArch][NFC] Revise instruction format to match lsx and lasx styles

Replace lengthy `0b...` binary form with a unified 32-bit hexadecimal representation for opcode. This reduces complexity when dealing with opcode discontinuities.
llvm · Jul 18, 2023 · 46aec7b · 46aec7b
1 parent b1d0bc0
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Showing 5 changed files with 471 additions and 512 deletions.
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
@@ -33,91 +33,91 @@ def loongarch_ftint : SDNode<"LoongArchISD::FTINT", SDT_LoongArchFTINT>;
 let Predicates = [HasBasicF] in {
 
 // Arithmetic Operation Instructions
-def FADD_S : FP_ALU_3R<0b00000001000000001, FPR32>;
-def FSUB_S : FP_ALU_3R<0b00000001000000101, FPR32>;
-def FMUL_S : FP_ALU_3R<0b00000001000001001, FPR32>;
-def FDIV_S : FP_ALU_3R<0b00000001000001101, FPR32>;
-def FMADD_S  : FP_ALU_4R<0b000010000001, FPR32>;
-def FMSUB_S  : FP_ALU_4R<0b000010000101, FPR32>;
-def FNMADD_S : FP_ALU_4R<0b000010001001, FPR32>;
-def FNMSUB_S : FP_ALU_4R<0b000010001101, FPR32>;
-def FMAX_S  : FP_ALU_3R<0b00000001000010001, FPR32>;
-def FMIN_S  : FP_ALU_3R<0b00000001000010101, FPR32>;
-def FMAXA_S : FP_ALU_3R<0b00000001000011001, FPR32>;
-def FMINA_S : FP_ALU_3R<0b00000001000011101, FPR32>;
-def FABS_S   : FP_ALU_2R<0b0000000100010100000001, FPR32>;
-def FNEG_S   : FP_ALU_2R<0b0000000100010100000101, FPR32>;
-def FSQRT_S  : FP_ALU_2R<0b0000000100010100010001, FPR32>;
-def FRECIP_S : FP_ALU_2R<0b0000000100010100010101, FPR32>;
-def FRSQRT_S : FP_ALU_2R<0b0000000100010100011001, FPR32>;
-def FSCALEB_S : FP_ALU_3R<0b00000001000100001, FPR32>;
-def FLOGB_S   : FP_ALU_2R<0b0000000100010100001001, FPR32>;
-def FCOPYSIGN_S : FP_ALU_3R<0b00000001000100101, FPR32>;
-def FCLASS_S  : FP_ALU_2R<0b0000000100010100001101, FPR32>;
+def FADD_S : FP_ALU_3R<0x01008000>;
+def FSUB_S : FP_ALU_3R<0x01028000>;
+def FMUL_S : FP_ALU_3R<0x01048000>;
+def FDIV_S : FP_ALU_3R<0x01068000>;
+def FMADD_S  : FP_ALU_4R<0x08100000>;
+def FMSUB_S  : FP_ALU_4R<0x08500000>;
+def FNMADD_S : FP_ALU_4R<0x08900000>;
+def FNMSUB_S : FP_ALU_4R<0x08d00000>;
+def FMAX_S  : FP_ALU_3R<0x01088000>;
+def FMIN_S  : FP_ALU_3R<0x010a8000>;
+def FMAXA_S : FP_ALU_3R<0x010c8000>;
+def FMINA_S : FP_ALU_3R<0x010e8000>;
+def FABS_S   : FP_ALU_2R<0x01140400>;
+def FNEG_S   : FP_ALU_2R<0x01141400>;
+def FSQRT_S  : FP_ALU_2R<0x01144400>;
+def FRECIP_S : FP_ALU_2R<0x01145400>;
+def FRSQRT_S : FP_ALU_2R<0x01146400>;
+def FSCALEB_S : FP_ALU_3R<0x01108000>;
+def FLOGB_S   : FP_ALU_2R<0x01142400>;
+def FCOPYSIGN_S : FP_ALU_3R<0x01128000>;
+def FCLASS_S  : FP_ALU_2R<0x01143400>;
 
 
 // Comparison Instructions
-def FCMP_CAF_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CAF, FPR32>;
-def FCMP_CUN_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUN, FPR32>;
-def FCMP_CEQ_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CEQ, FPR32>;
-def FCMP_CUEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUEQ, FPR32>;
-def FCMP_CLT_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CLT, FPR32>;
-def FCMP_CULT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CULT, FPR32>;
-def FCMP_CLE_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CLE, FPR32>;
-def FCMP_CULE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CULE, FPR32>;
-def FCMP_CNE_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CNE, FPR32>;
-def FCMP_COR_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_COR, FPR32>;
-def FCMP_CUNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUNE, FPR32>;
-def FCMP_SAF_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SAF, FPR32>;
-def FCMP_SUN_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUN, FPR32>;
-def FCMP_SEQ_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SEQ, FPR32>;
-def FCMP_SUEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUEQ, FPR32>;
-def FCMP_SLT_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SLT, FPR32>;
-def FCMP_SULT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SULT, FPR32>;
-def FCMP_SLE_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SLE, FPR32>;
-def FCMP_SULE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SULE, FPR32>;
-def FCMP_SNE_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SNE, FPR32>;
-def FCMP_SOR_S  : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SOR, FPR32>;
-def FCMP_SUNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUNE, FPR32>;
+def FCMP_CAF_S  : FP_CMP<0x0c100000>;
+def FCMP_CUN_S  : FP_CMP<0x0c140000>;
+def FCMP_CEQ_S  : FP_CMP<0x0c120000>;
+def FCMP_CUEQ_S : FP_CMP<0x0c160000>;
+def FCMP_CLT_S  : FP_CMP<0x0c110000>;
+def FCMP_CULT_S : FP_CMP<0x0c150000>;
+def FCMP_CLE_S  : FP_CMP<0x0c130000>;
+def FCMP_CULE_S : FP_CMP<0x0c170000>;
+def FCMP_CNE_S  : FP_CMP<0x0c180000>;
+def FCMP_COR_S  : FP_CMP<0x0c1a0000>;
+def FCMP_CUNE_S : FP_CMP<0x0c1c0000>;
+def FCMP_SAF_S  : FP_CMP<0x0c108000>;
+def FCMP_SUN_S  : FP_CMP<0x0c148000>;
+def FCMP_SEQ_S  : FP_CMP<0x0c128000>;
+def FCMP_SUEQ_S : FP_CMP<0x0c168000>;
+def FCMP_SLT_S  : FP_CMP<0x0c118000>;
+def FCMP_SULT_S : FP_CMP<0x0c158000>;
+def FCMP_SLE_S  : FP_CMP<0x0c138000>;
+def FCMP_SULE_S : FP_CMP<0x0c178000>;
+def FCMP_SNE_S  : FP_CMP<0x0c188000>;
+def FCMP_SOR_S  : FP_CMP<0x0c1a8000>;
+def FCMP_SUNE_S : FP_CMP<0x0c1c8000>;
 
 // Conversion Instructions
-def FFINT_S_W    : FP_CONV<0b0000000100011101000100, FPR32, FPR32>;
-def FTINT_W_S    : FP_CONV<0b0000000100011011000001, FPR32, FPR32>;
-def FTINTRM_W_S  : FP_CONV<0b0000000100011010000001, FPR32, FPR32>;
-def FTINTRP_W_S  : FP_CONV<0b0000000100011010010001, FPR32, FPR32>;
-def FTINTRZ_W_S  : FP_CONV<0b0000000100011010100001, FPR32, FPR32>;
-def FTINTRNE_W_S : FP_CONV<0b0000000100011010110001, FPR32, FPR32>;
-def FRINT_S      : FP_CONV<0b0000000100011110010001, FPR32, FPR32>;
+def FFINT_S_W    : FP_CONV<0x011d1000>;
+def FTINT_W_S    : FP_CONV<0x011b0400>;
+def FTINTRM_W_S  : FP_CONV<0x011a0400>;
+def FTINTRP_W_S  : FP_CONV<0x011a4400>;
+def FTINTRZ_W_S  : FP_CONV<0x011a8400>;
+def FTINTRNE_W_S : FP_CONV<0x011ac400>;
+def FRINT_S      : FP_CONV<0x011e4400>;
 
 // Move Instructions
-def FSEL_xS    : FP_SEL<0b00001101000000, FPR32>;
-def FMOV_S     : FP_MOV<0b0000000100010100100101, FPR32, FPR32>;
-def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, FPR32, GPR>;
-def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, GPR, FPR32>;
+def FSEL_xS    : FP_SEL<0x0d000000>;
+def FMOV_S     : FP_MOV<0x01149400>;
+def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>;
+def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>;
 let hasSideEffects = 1 in {
-def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, FCSR, GPR>;
-def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, GPR, FCSR>;
+def MOVGR2FCSR : FP_MOV<0x0114c000, FCSR, GPR>;
+def MOVFCSR2GR : FP_MOV<0x0114c800, GPR, FCSR>;
 } // hasSideEffects = 1
-def MOVFR2CF_xS : FP_MOV<0b0000000100010100110100, CFR, FPR32>;
-def MOVCF2FR_xS : FP_MOV<0b0000000100010100110101, FPR32, CFR>;
-def MOVGR2CF    : FP_MOV<0b0000000100010100110110, CFR, GPR>;
-def MOVCF2GR    : FP_MOV<0b0000000100010100110111, GPR, CFR>;
+def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>;
+def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>;
+def MOVGR2CF    : FP_MOV<0x0114d800, CFR, GPR>;
+def MOVCF2GR    : FP_MOV<0x0114dc00, GPR, CFR>;
 
 // Branch Instructions
-def BCEQZ : FP_BRANCH<0b01001000>;
-def BCNEZ : FP_BRANCH<0b01001001>;
+def BCEQZ : FP_BRANCH<0x48000000>;
+def BCNEZ : FP_BRANCH<0x48000100>;
 
 // Common Memory Access Instructions
-def FLD_S : FP_LOAD_2RI12<0b0010101100, FPR32>;
-def FST_S : FP_STORE_2RI12<0b0010101101, FPR32>;
-def FLDX_S : FP_LOAD_3R<0b00111000001100000, FPR32>;
-def FSTX_S : FP_STORE_3R<0b00111000001110000, FPR32>;
+def FLD_S : FP_LOAD_2RI12<0x2b000000>;
+def FST_S : FP_STORE_2RI12<0x2b400000>;
+def FLDX_S : FP_LOAD_3R<0x38300000>;
+def FSTX_S : FP_STORE_3R<0x38380000>;
 
 // Bound Check Memory Access Instructions
-def FLDGT_S : FP_LOAD_3R<0b00111000011101000, FPR32>;
-def FLDLE_S : FP_LOAD_3R<0b00111000011101010, FPR32>;
-def FSTGT_S : FP_STORE_3R<0b00111000011101100, FPR32>;
-def FSTLE_S : FP_STORE_3R<0b00111000011101110, FPR32>;
+def FLDGT_S : FP_LOAD_3R<0x38740000>;
+def FLDLE_S : FP_LOAD_3R<0x38750000>;
+def FSTGT_S : FP_STORE_3R<0x38760000>;
+def FSTLE_S : FP_STORE_3R<0x38770000>;
 
 // Pseudo instructions for spill/reload CFRs.
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in

diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
@@ -17,111 +17,111 @@
 let Predicates = [HasBasicD] in {
 
 // Arithmetic Operation Instructions
-def FADD_D : FP_ALU_3R<0b00000001000000010, FPR64>;
-def FSUB_D : FP_ALU_3R<0b00000001000000110, FPR64>;
-def FMUL_D : FP_ALU_3R<0b00000001000001010, FPR64>;
-def FDIV_D : FP_ALU_3R<0b00000001000001110, FPR64>;
-def FMADD_D  : FP_ALU_4R<0b000010000010, FPR64>;
-def FMSUB_D  : FP_ALU_4R<0b000010000110, FPR64>;
-def FNMADD_D : FP_ALU_4R<0b000010001010, FPR64>;
-def FNMSUB_D : FP_ALU_4R<0b000010001110, FPR64>;
-def FMAX_D  : FP_ALU_3R<0b00000001000010010, FPR64>;
-def FMIN_D  : FP_ALU_3R<0b00000001000010110, FPR64>;
-def FMAXA_D : FP_ALU_3R<0b00000001000011010, FPR64>;
-def FMINA_D : FP_ALU_3R<0b00000001000011110, FPR64>;
-def FABS_D   : FP_ALU_2R<0b0000000100010100000010, FPR64>;
-def FNEG_D   : FP_ALU_2R<0b0000000100010100000110, FPR64>;
-def FSQRT_D  : FP_ALU_2R<0b0000000100010100010010, FPR64>;
-def FRECIP_D : FP_ALU_2R<0b0000000100010100010110, FPR64>;
-def FRSQRT_D : FP_ALU_2R<0b0000000100010100011010, FPR64>;
-def FSCALEB_D : FP_ALU_3R<0b00000001000100010, FPR64>;
-def FLOGB_D   : FP_ALU_2R<0b0000000100010100001010, FPR64>;
-def FCOPYSIGN_D : FP_ALU_3R<0b00000001000100110, FPR64>;
-def FCLASS_D  : FP_ALU_2R<0b0000000100010100001110, FPR64>;
+def FADD_D : FP_ALU_3R<0x01010000, FPR64>;
+def FSUB_D : FP_ALU_3R<0x01030000, FPR64>;
+def FMUL_D : FP_ALU_3R<0x01050000, FPR64>;
+def FDIV_D : FP_ALU_3R<0x01070000, FPR64>;
+def FMADD_D  : FP_ALU_4R<0x08200000, FPR64>;
+def FMSUB_D  : FP_ALU_4R<0x08600000, FPR64>;
+def FNMADD_D : FP_ALU_4R<0x08a00000, FPR64>;
+def FNMSUB_D : FP_ALU_4R<0x08e00000, FPR64>;
+def FMAX_D  : FP_ALU_3R<0x01090000, FPR64>;
+def FMIN_D  : FP_ALU_3R<0x010b0000, FPR64>;
+def FMAXA_D : FP_ALU_3R<0x010d0000, FPR64>;
+def FMINA_D : FP_ALU_3R<0x010f0000, FPR64>;
+def FABS_D   : FP_ALU_2R<0x01140800, FPR64>;
+def FNEG_D   : FP_ALU_2R<0x01141800, FPR64>;
+def FSQRT_D  : FP_ALU_2R<0x01144800, FPR64>;
+def FRECIP_D : FP_ALU_2R<0x01145800, FPR64>;
+def FRSQRT_D : FP_ALU_2R<0x01146800, FPR64>;
+def FSCALEB_D : FP_ALU_3R<0x01110000, FPR64>;
+def FLOGB_D   : FP_ALU_2R<0x01142800, FPR64>;
+def FCOPYSIGN_D : FP_ALU_3R<0x01130000, FPR64>;
+def FCLASS_D  : FP_ALU_2R<0x01143800, FPR64>;
 
 // Comparison Instructions
-def FCMP_CAF_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CAF, FPR64>;
-def FCMP_CUN_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUN, FPR64>;
-def FCMP_CEQ_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CEQ, FPR64>;
-def FCMP_CUEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUEQ, FPR64>;
-def FCMP_CLT_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CLT, FPR64>;
-def FCMP_CULT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CULT, FPR64>;
-def FCMP_CLE_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CLE, FPR64>;
-def FCMP_CULE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CULE, FPR64>;
-def FCMP_CNE_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CNE, FPR64>;
-def FCMP_COR_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_COR, FPR64>;
-def FCMP_CUNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUNE, FPR64>;
-def FCMP_SAF_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SAF, FPR64>;
-def FCMP_SUN_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUN, FPR64>;
-def FCMP_SEQ_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SEQ, FPR64>;
-def FCMP_SUEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUEQ, FPR64>;
-def FCMP_SLT_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SLT, FPR64>;
-def FCMP_SULT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SULT, FPR64>;
-def FCMP_SLE_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SLE, FPR64>;
-def FCMP_SULE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SULE, FPR64>;
-def FCMP_SNE_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SNE, FPR64>;
-def FCMP_SOR_D  : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SOR, FPR64>;
-def FCMP_SUNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUNE, FPR64>;
+def FCMP_CAF_D  : FP_CMP<0x0c200000, FPR64>;
+def FCMP_CUN_D  : FP_CMP<0x0c240000, FPR64>;
+def FCMP_CEQ_D  : FP_CMP<0x0c220000, FPR64>;
+def FCMP_CUEQ_D : FP_CMP<0x0c260000, FPR64>;
+def FCMP_CLT_D  : FP_CMP<0x0c210000, FPR64>;
+def FCMP_CULT_D : FP_CMP<0x0c250000, FPR64>;
+def FCMP_CLE_D  : FP_CMP<0x0c230000, FPR64>;
+def FCMP_CULE_D : FP_CMP<0x0c270000, FPR64>;
+def FCMP_CNE_D  : FP_CMP<0x0c280000, FPR64>;
+def FCMP_COR_D  : FP_CMP<0x0c2a0000, FPR64>;
+def FCMP_CUNE_D : FP_CMP<0x0c2c0000, FPR64>;
+def FCMP_SAF_D  : FP_CMP<0x0c208000, FPR64>;
+def FCMP_SUN_D  : FP_CMP<0x0c248000, FPR64>;
+def FCMP_SEQ_D  : FP_CMP<0x0c228000, FPR64>;
+def FCMP_SUEQ_D : FP_CMP<0x0c268000, FPR64>;
+def FCMP_SLT_D  : FP_CMP<0x0c218000, FPR64>;
+def FCMP_SULT_D : FP_CMP<0x0c258000, FPR64>;
+def FCMP_SLE_D  : FP_CMP<0x0c238000, FPR64>;
+def FCMP_SULE_D : FP_CMP<0x0c278000, FPR64>;
+def FCMP_SNE_D  : FP_CMP<0x0c288000, FPR64>;
+def FCMP_SOR_D  : FP_CMP<0x0c2a8000, FPR64>;
+def FCMP_SUNE_D : FP_CMP<0x0c2c8000, FPR64>;
 
 // Conversion Instructions
-def FFINT_S_L : FP_CONV<0b0000000100011101000110, FPR32, FPR64>;
-def FTINT_L_S : FP_CONV<0b0000000100011011001001, FPR64, FPR32>;
-def FTINTRM_L_S : FP_CONV<0b0000000100011010001001, FPR64, FPR32>;
-def FTINTRP_L_S : FP_CONV<0b0000000100011010011001, FPR64, FPR32>;
-def FTINTRZ_L_S : FP_CONV<0b0000000100011010101001, FPR64, FPR32>;
-def FTINTRNE_L_S : FP_CONV<0b0000000100011010111001, FPR64, FPR32>;
-def FCVT_S_D : FP_CONV<0b0000000100011001000110, FPR32, FPR64>;
-def FCVT_D_S : FP_CONV<0b0000000100011001001001, FPR64, FPR32>;
-def FFINT_D_W : FP_CONV<0b0000000100011101001000, FPR64, FPR32>;
-def FFINT_D_L : FP_CONV<0b0000000100011101001010, FPR64, FPR64>;
-def FTINT_W_D : FP_CONV<0b0000000100011011000010, FPR32, FPR64>;
-def FTINT_L_D : FP_CONV<0b0000000100011011001010, FPR64, FPR64>;
-def FTINTRM_W_D : FP_CONV<0b0000000100011010000010, FPR32, FPR64>;
-def FTINTRM_L_D : FP_CONV<0b0000000100011010001010, FPR64, FPR64>;
-def FTINTRP_W_D : FP_CONV<0b0000000100011010010010, FPR32, FPR64>;
-def FTINTRP_L_D : FP_CONV<0b0000000100011010011010, FPR64, FPR64>;
-def FTINTRZ_W_D : FP_CONV<0b0000000100011010100010, FPR32, FPR64>;
-def FTINTRZ_L_D : FP_CONV<0b0000000100011010101010, FPR64, FPR64>;
-def FTINTRNE_W_D : FP_CONV<0b0000000100011010110010, FPR32, FPR64>;
-def FTINTRNE_L_D : FP_CONV<0b0000000100011010111010, FPR64, FPR64>;
-def FRINT_D : FP_CONV<0b0000000100011110010010, FPR64, FPR64>;
+def FFINT_S_L : FP_CONV<0x011d1800, FPR32, FPR64>;
+def FTINT_L_S : FP_CONV<0x011b2400, FPR64, FPR32>;
+def FTINTRM_L_S : FP_CONV<0x011a2400, FPR64, FPR32>;
+def FTINTRP_L_S : FP_CONV<0x011a6400, FPR64, FPR32>;
+def FTINTRZ_L_S : FP_CONV<0x011aa400, FPR64, FPR32>;
+def FTINTRNE_L_S : FP_CONV<0x011ae400, FPR64, FPR32>;
+def FCVT_S_D : FP_CONV<0x01191800, FPR32, FPR64>;
+def FCVT_D_S : FP_CONV<0x01192400, FPR64, FPR32>;
+def FFINT_D_W : FP_CONV<0x011d2000, FPR64, FPR32>;
+def FFINT_D_L : FP_CONV<0x011d2800, FPR64, FPR64>;
+def FTINT_W_D : FP_CONV<0x011b0800, FPR32, FPR64>;
+def FTINT_L_D : FP_CONV<0x011b2800, FPR64, FPR64>;
+def FTINTRM_W_D : FP_CONV<0x011a0800, FPR32, FPR64>;
+def FTINTRM_L_D : FP_CONV<0x011a2800, FPR64, FPR64>;
+def FTINTRP_W_D : FP_CONV<0x011a4800, FPR32, FPR64>;
+def FTINTRP_L_D : FP_CONV<0x011a6800, FPR64, FPR64>;
+def FTINTRZ_W_D : FP_CONV<0x011a8800, FPR32, FPR64>;
+def FTINTRZ_L_D : FP_CONV<0x011aa800, FPR64, FPR64>;
+def FTINTRNE_W_D : FP_CONV<0x011ac800, FPR32, FPR64>;
+def FTINTRNE_L_D : FP_CONV<0x011ae800, FPR64, FPR64>;
+def FRINT_D : FP_CONV<0x011e4800, FPR64, FPR64>;
 
 // Move Instructions
-def FMOV_D        : FP_MOV<0b0000000100010100100110, FPR64, FPR64>;
-def MOVFRH2GR_S   : FP_MOV<0b0000000100010100101111, GPR, FPR64>;
+def FMOV_D        : FP_MOV<0x01149800, FPR64, FPR64>;
+def MOVFRH2GR_S   : FP_MOV<0x0114bc00, GPR, FPR64>;
 let isCodeGenOnly = 1 in {
-def MOVFR2GR_S_64 : FP_MOV<0b0000000100010100101101, GPR, FPR64>;
-def FSEL_xD : FP_SEL<0b00001101000000, FPR64>;
+def MOVFR2GR_S_64 : FP_MOV<0x0114b400, GPR, FPR64>;
+def FSEL_xD : FP_SEL<0x0d000000, FPR64>;
 } // isCodeGenOnly = 1
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out" in {
-def MOVGR2FRH_W : FPFmtMOV<0b0000000100010100101011, (outs FPR64:$out),
+def MOVGR2FRH_W : FPFmtMOV<0x0114ac00, (outs FPR64:$out),
                            (ins FPR64:$dst, GPR:$src),
                            "$dst, $src">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out"
 
 // Common Memory Access Instructions
-def FLD_D : FP_LOAD_2RI12<0b0010101110, FPR64>;
-def FST_D : FP_STORE_2RI12<0b0010101111, FPR64>;
-def FLDX_D : FP_LOAD_3R<0b00111000001101000, FPR64>;
-def FSTX_D : FP_STORE_3R<0b00111000001111000, FPR64>;
+def FLD_D : FP_LOAD_2RI12<0x2b800000, FPR64>;
+def FST_D : FP_STORE_2RI12<0x2bc00000, FPR64>;
+def FLDX_D : FP_LOAD_3R<0x38340000, FPR64>;
+def FSTX_D : FP_STORE_3R<0x383c0000, FPR64>;
 
 // Bound Check Memory Access Instructions
-def FLDGT_D : FP_LOAD_3R<0b00111000011101001, FPR64>;
-def FLDLE_D : FP_LOAD_3R<0b00111000011101011, FPR64>;
-def FSTGT_D : FP_STORE_3R<0b00111000011101101, FPR64>;
-def FSTLE_D : FP_STORE_3R<0b00111000011101111, FPR64>;
+def FLDGT_D : FP_LOAD_3R<0x38748000, FPR64>;
+def FLDLE_D : FP_LOAD_3R<0x38758000, FPR64>;
+def FSTGT_D : FP_STORE_3R<0x38768000, FPR64>;
+def FSTLE_D : FP_STORE_3R<0x38778000, FPR64>;
 
 } // Predicates = [HasBasicD]
 
 // Instructions only available on LA64
 let Predicates = [HasBasicD, IsLA64] in {
-def MOVGR2FR_D  : FP_MOV<0b0000000100010100101010, FPR64, GPR>;
-def MOVFR2GR_D  : FP_MOV<0b0000000100010100101110, GPR, FPR64>;
+def MOVGR2FR_D  : FP_MOV<0x0114a800, FPR64, GPR>;
+def MOVFR2GR_D  : FP_MOV<0x0114b800, GPR, FPR64>;
 } // Predicates = [HasBasicD, IsLA64]
 
 // Instructions only available on LA32
 let Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1 in {
-def MOVGR2FR_W_64 : FP_MOV<0b0000000100010100101001, FPR64, GPR>;
+def MOVGR2FR_W_64 : FP_MOV<0x0114a400, FPR64, GPR>;
 } // Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1
 
 //===----------------------------------------------------------------------===//