[PhaseOrdering] add test for loop-idiom-recognize + tailcall; NFC

llvm/test/Transforms/PhaseOrdering/memset-tail.ll

@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
+
+define void @PR47852(ptr noundef %d, i32 noundef %c) {
+; CHECK-LABEL: @PR47852(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP_NOT1:%.*]] = icmp eq i32 [[C:%.*]], 0
+; CHECK-NEXT:    br i1 [[CMP_NOT1]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
+; CHECK:       while.body.preheader:
+; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[C]] to i64
+; CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 1 [[D:%.*]], i8 0, i64 [[TMP0]], i1 false)
+; CHECK-NEXT:    br label [[WHILE_END]]
+; CHECK:       while.end:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %while.cond
+
+while.cond:
+  %c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %while.body ]
+  %d.addr.0 = phi ptr [ %d, %entry ], [ %incdec.ptr, %while.body ]
+  %dec = add i32 %c.addr.0, -1
+  %cmp = icmp ugt i32 %c.addr.0, 0
+  br i1 %cmp, label %while.body, label %while.end
+
+while.body:
+  %incdec.ptr = getelementptr inbounds i8, ptr %d.addr.0, i32 1
+  store i8 0, ptr %d.addr.0, align 1
+  br label %while.cond
+
+while.end:
+  ret void
+}