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[AMDGPU] Add legality check when folding short 64-bit literals (#69391)
We can only fold it if it can fit into 32-bit. I believe it did not trigger yet because we do not select 64-bit literals generally.
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llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 | ||
# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s | ||
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--- | ||
name: no_fold_fp_64bit_literal_sgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
; GCN-LABEL: name: no_fold_fp_64bit_literal_sgpr | ||
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF | ||
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1311768467750121200 | ||
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, [[S_MOV_B64_]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec | ||
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]] | ||
%0:vreg_64 = IMPLICIT_DEF | ||
%1:sreg_64 = S_MOV_B64 1311768467750121200 | ||
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec | ||
SI_RETURN_TO_EPILOG %2 | ||
... | ||
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--- | ||
name: no_fold_fp_64bit_literal_vgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
; GCN-LABEL: name: no_fold_fp_64bit_literal_vgpr | ||
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF | ||
; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec | ||
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, [[V_MOV_B]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec | ||
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]] | ||
%0:vreg_64 = IMPLICIT_DEF | ||
%1:vreg_64 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec | ||
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec | ||
SI_RETURN_TO_EPILOG %2 | ||
... | ||
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--- | ||
name: fold_fp_32bit_literal_sgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
; GCN-LABEL: name: fold_fp_32bit_literal_sgpr | ||
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF | ||
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, 4636737291354636288, 0, [[DEF]], 0, 0, implicit $mode, implicit $exec | ||
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]] | ||
%0:vreg_64 = IMPLICIT_DEF | ||
%1:sreg_64 = S_MOV_B64 4636737291354636288 | ||
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec | ||
SI_RETURN_TO_EPILOG %2 | ||
... | ||
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--- | ||
name: no_fold_int_64bit_literal_sgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
; GCN-LABEL: name: no_fold_int_64bit_literal_sgpr | ||
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF | ||
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1311768467750121200 | ||
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], [[S_MOV_B64_]], implicit-def $scc | ||
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]] | ||
%0:sreg_64 = IMPLICIT_DEF | ||
%1:sreg_64 = S_MOV_B64 1311768467750121200 | ||
%2:sreg_64 = S_AND_B64 %0, %1, implicit-def $scc | ||
SI_RETURN_TO_EPILOG %2 | ||
... | ||
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--- | ||
name: fold_int_32bit_literal_sgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
; GCN-LABEL: name: fold_int_32bit_literal_sgpr | ||
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF | ||
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], 2147483647, implicit-def $scc | ||
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]] | ||
%0:sreg_64 = IMPLICIT_DEF | ||
%1:sreg_64 = S_MOV_B64 2147483647 | ||
%2:sreg_64 = S_AND_B64 %0, %1, implicit-def $scc | ||
SI_RETURN_TO_EPILOG %2 | ||
... | ||
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--- | ||
name: fold_uint_32bit_literal_sgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
; GCN-LABEL: name: fold_uint_32bit_literal_sgpr | ||
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF | ||
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], 4294967295, implicit-def $scc | ||
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]] | ||
%0:sreg_64 = IMPLICIT_DEF | ||
%1:sreg_64 = S_MOV_B64 4294967295 | ||
%2:sreg_64 = S_AND_B64 %0, %1, implicit-def $scc | ||
SI_RETURN_TO_EPILOG %2 | ||
... | ||
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--- | ||
name: no_fold_v2fp_64bit_literal_sgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
%0:vreg_64 = IMPLICIT_DEF | ||
%1:vreg_64 = V_MOV_B64_PSEUDO 4629700418019000320, implicit $exec | ||
%2:vreg_64 = V_PK_ADD_F32 0, %0, 0, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec | ||
SI_RETURN_TO_EPILOG %2 | ||
... | ||
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--- | ||
name: fold_v2fp_32bit_literal_sgpr | ||
tracksRegLiveness: true | ||
body: | | ||
bb.0: | ||
%0:vreg_64 = IMPLICIT_DEF | ||
%1:vreg_64 = V_MOV_B64_PSEUDO 1065353216, implicit $exec | ||
%2:vreg_64 = V_PK_ADD_F32 0, %0, 0, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec | ||
SI_RETURN_TO_EPILOG %2 | ||
... |