[AMDGPU][GFX9][DOC][NFC] Update assembler syntax description

Summary of changes: - Updated MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Updated SMEM syntax (see https://reviews.llvm.org/D127314). - Enabled src0=literal for v_madak*, v_madmk* (see https://reviews.llvm.org/D111067). - Removed SYSMSG_OP_HOST_TRAP_ACK message. - Minor bug fixing and improvements.
llvm · Jun 27, 2022 · 480f3e0 · 480f3e0
1 parent 94fbb14
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diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
diff --git a/llvm/docs/AMDGPU/gfx9_hwreg.rst b/llvm/docs/AMDGPU/gfx9_hwreg.rst
@@ -41,22 +41,22 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
 
 Defined register *names* include:
 
-    =================== ==========================================
-    Name                Description
-    =================== ==========================================
-    HW_REG_MODE         Shader writeable mode bits.
-    HW_REG_STATUS       Shader read-only status.
-    HW_REG_TRAPSTS      Trap status.
-    HW_REG_HW_ID        Id of wave, simd, compute unit, etc.
-    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
-    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
-    HW_REG_IB_STS       Counters of outstanding instructions.
-    HW_REG_SH_MEM_BASES Memory aperture.
-    HW_REG_TBA_LO       tba_lo register.
-    HW_REG_TBA_HI       tba_hi register.
-    HW_REG_TMA_LO       tma_lo register.
-    HW_REG_TMA_HI       tma_hi register.
-    =================== ==========================================
+    ============================== ==========================================
+    Name                           Description
+    ============================== ==========================================
+    HW_REG_MODE                    Shader writeable mode bits.
+    HW_REG_STATUS                  Shader read-only status.
+    HW_REG_TRAPSTS                 Trap status.
+    HW_REG_HW_ID                   Id of wave, simd, compute unit, etc.
+    HW_REG_GPR_ALLOC               Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC               Per-wave LDS allocation.
+    HW_REG_IB_STS                  Counters of outstanding instructions.
+    HW_REG_SH_MEM_BASES            Memory aperture.
+    HW_REG_TBA_LO                  tba_lo register.
+    HW_REG_TBA_HI                  tba_hi register.
+    HW_REG_TMA_LO                  tma_lo register.
+    HW_REG_TMA_HI                  tma_hi register.
+    ============================== ==========================================
 
 Examples:
 

diff --git a/llvm/docs/AMDGPU/gfx9_imm16_2.rst b/llvm/docs/AMDGPU/gfx9_imm16_2.rst
diff --git a/llvm/docs/AMDGPU/gfx9_imm16.rst → llvm/docs/AMDGPU/gfx9_imm16_73139a.rst b/llvm/docs/AMDGPU/gfx9_imm16.rst → llvm/docs/AMDGPU/gfx9_imm16_73139a.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_imm16:
+.. _amdgpu_synid_gfx9_imm16_73139a:
 
 imm16
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_imm16_1.rst → llvm/docs/AMDGPU/gfx9_imm16_a04fb3.rst b/llvm/docs/AMDGPU/gfx9_imm16_1.rst → llvm/docs/AMDGPU/gfx9_imm16_a04fb3.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_imm16_1:
+.. _amdgpu_synid_gfx9_imm16_a04fb3:
 
 imm16
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_m.rst → llvm/docs/AMDGPU/gfx9_m_254bcb.rst b/llvm/docs/AMDGPU/gfx9_m.rst → llvm/docs/AMDGPU/gfx9_m_254bcb.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_m:
+.. _amdgpu_synid_gfx9_m_254bcb:
 
 m
 =

diff --git a/llvm/docs/AMDGPU/gfx9_m_1.rst → llvm/docs/AMDGPU/gfx9_m_f5d306.rst b/llvm/docs/AMDGPU/gfx9_m_1.rst → llvm/docs/AMDGPU/gfx9_m_f5d306.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_m_1:
+.. _amdgpu_synid_gfx9_m_f5d306:
 
 m
 =

diff --git a/llvm/docs/AMDGPU/gfx9_msg.rst b/llvm/docs/AMDGPU/gfx9_msg.rst
@@ -67,7 +67,6 @@ Each message type supports specific operations:
     MSG_GET_DOORBELL       10         \-                             \-           \-
     MSG_SYSMSG             15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
     \                                 SYSMSG_OP_REG_RD               2            \-
-    \                                 SYSMSG_OP_HOST_TRAP_ACK        3            \-
     \                                 SYSMSG_OP_TTRACE_PC            4            \-
     ====================== ========== ============================== ============ ==========
 

diff --git a/llvm/docs/AMDGPU/gfx9_opt_0d447d.rst b/llvm/docs/AMDGPU/gfx9_opt_0d447d.rst
@@ -0,0 +1,13 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx9_opt_0d447d:
+
+opt
+===
+
+This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
diff --git a/llvm/docs/AMDGPU/gfx9_opt.rst → llvm/docs/AMDGPU/gfx9_opt_847aed.rst b/llvm/docs/AMDGPU/gfx9_opt.rst → llvm/docs/AMDGPU/gfx9_opt_847aed.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_opt:
+.. _amdgpu_synid_gfx9_opt_847aed:
 
 opt
 ===

diff --git a/llvm/docs/AMDGPU/gfx9_saddr_1.rst → llvm/docs/AMDGPU/gfx9_saddr_6060e5.rst b/llvm/docs/AMDGPU/gfx9_saddr_1.rst → llvm/docs/AMDGPU/gfx9_saddr_6060e5.rst
@@ -5,14 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_saddr_1:
+.. _amdgpu_synid_gfx9_saddr_6060e5:
 
 saddr
 =====
 
 An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
 
-Either this operand or :ref:`vaddr<amdgpu_synid_gfx9_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
+Either this operand or :ref:`vaddr<amdgpu_synid_gfx9_vaddr_76b997>` must be set to :ref:`off<amdgpu_synid_off>`.
 
 *Size:* 1 dword.
 

diff --git a/llvm/docs/AMDGPU/gfx9_saddr.rst → llvm/docs/AMDGPU/gfx9_saddr_a37373.rst b/llvm/docs/AMDGPU/gfx9_saddr.rst → llvm/docs/AMDGPU/gfx9_saddr_a37373.rst
@@ -5,14 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_saddr:
+.. _amdgpu_synid_gfx9_saddr_a37373:
 
 saddr
 =====
 
 An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
 
-See :ref:`vaddr<amdgpu_synid_gfx9_vaddr_2>` for description of available addressing modes.
+See :ref:`vaddr<amdgpu_synid_gfx9_vaddr_0212e3>` for description of available addressing modes.
 
 *Size:* 2 dwords.
 

diff --git a/llvm/docs/AMDGPU/gfx9_sbase_1.rst → llvm/docs/AMDGPU/gfx9_sbase_010ce0.rst b/llvm/docs/AMDGPU/gfx9_sbase_1.rst → llvm/docs/AMDGPU/gfx9_sbase_010ce0.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sbase_1:
+.. _amdgpu_synid_gfx9_sbase_010ce0:
 
 sbase
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sbase.rst → llvm/docs/AMDGPU/gfx9_sbase_044055.rst b/llvm/docs/AMDGPU/gfx9_sbase.rst → llvm/docs/AMDGPU/gfx9_sbase_044055.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sbase:
+.. _amdgpu_synid_gfx9_sbase_044055:
 
 sbase
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sbase_2.rst → llvm/docs/AMDGPU/gfx9_sbase_0cd545.rst b/llvm/docs/AMDGPU/gfx9_sbase_2.rst → llvm/docs/AMDGPU/gfx9_sbase_0cd545.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sbase_2:
+.. _amdgpu_synid_gfx9_sbase_0cd545:
 
 sbase
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sdata_3.rst → llvm/docs/AMDGPU/gfx9_sdata_595c25.rst b/llvm/docs/AMDGPU/gfx9_sdata_3.rst → llvm/docs/AMDGPU/gfx9_sdata_595c25.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdata_3:
+.. _amdgpu_synid_gfx9_sdata_595c25:
 
 sdata
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sdata_5.rst → llvm/docs/AMDGPU/gfx9_sdata_7cbd60.rst b/llvm/docs/AMDGPU/gfx9_sdata_5.rst → llvm/docs/AMDGPU/gfx9_sdata_7cbd60.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdata_5:
+.. _amdgpu_synid_gfx9_sdata_7cbd60:
 
 sdata
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sdata.rst → llvm/docs/AMDGPU/gfx9_sdata_aefe00.rst b/llvm/docs/AMDGPU/gfx9_sdata.rst → llvm/docs/AMDGPU/gfx9_sdata_aefe00.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdata:
+.. _amdgpu_synid_gfx9_sdata_aefe00:
 
 sdata
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sdata_2.rst → llvm/docs/AMDGPU/gfx9_sdata_c6aec1.rst b/llvm/docs/AMDGPU/gfx9_sdata_2.rst → llvm/docs/AMDGPU/gfx9_sdata_c6aec1.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdata_2:
+.. _amdgpu_synid_gfx9_sdata_c6aec1:
 
 sdata
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sdata_4.rst → llvm/docs/AMDGPU/gfx9_sdata_e9f591.rst b/llvm/docs/AMDGPU/gfx9_sdata_4.rst → llvm/docs/AMDGPU/gfx9_sdata_e9f591.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdata_4:
+.. _amdgpu_synid_gfx9_sdata_e9f591:
 
 sdata
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sdata_1.rst → llvm/docs/AMDGPU/gfx9_sdata_eb6f2a.rst b/llvm/docs/AMDGPU/gfx9_sdata_1.rst → llvm/docs/AMDGPU/gfx9_sdata_eb6f2a.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdata_1:
+.. _amdgpu_synid_gfx9_sdata_eb6f2a:
 
 sdata
 =====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst_5.rst → llvm/docs/AMDGPU/gfx9_sdst_06b266.rst b/llvm/docs/AMDGPU/gfx9_sdst_5.rst → llvm/docs/AMDGPU/gfx9_sdst_06b266.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst_5:
+.. _amdgpu_synid_gfx9_sdst_06b266:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst_3.rst → llvm/docs/AMDGPU/gfx9_sdst_0804b1.rst b/llvm/docs/AMDGPU/gfx9_sdst_3.rst → llvm/docs/AMDGPU/gfx9_sdst_0804b1.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst_3:
+.. _amdgpu_synid_gfx9_sdst_0804b1:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst_4.rst → llvm/docs/AMDGPU/gfx9_sdst_362c37.rst b/llvm/docs/AMDGPU/gfx9_sdst_4.rst → llvm/docs/AMDGPU/gfx9_sdst_362c37.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst_4:
+.. _amdgpu_synid_gfx9_sdst_362c37:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst_1.rst → llvm/docs/AMDGPU/gfx9_sdst_3bc700.rst b/llvm/docs/AMDGPU/gfx9_sdst_1.rst → llvm/docs/AMDGPU/gfx9_sdst_3bc700.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst_1:
+.. _amdgpu_synid_gfx9_sdst_3bc700:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst_7.rst → llvm/docs/AMDGPU/gfx9_sdst_59204c.rst b/llvm/docs/AMDGPU/gfx9_sdst_7.rst → llvm/docs/AMDGPU/gfx9_sdst_59204c.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst_7:
+.. _amdgpu_synid_gfx9_sdst_59204c:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst_2.rst → llvm/docs/AMDGPU/gfx9_sdst_718cc4.rst b/llvm/docs/AMDGPU/gfx9_sdst_2.rst → llvm/docs/AMDGPU/gfx9_sdst_718cc4.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst_2:
+.. _amdgpu_synid_gfx9_sdst_718cc4:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst.rst → llvm/docs/AMDGPU/gfx9_sdst_94342d.rst b/llvm/docs/AMDGPU/gfx9_sdst.rst → llvm/docs/AMDGPU/gfx9_sdst_94342d.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst:
+.. _amdgpu_synid_gfx9_sdst_94342d:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_sdst_6.rst → llvm/docs/AMDGPU/gfx9_sdst_a319e6.rst b/llvm/docs/AMDGPU/gfx9_sdst_6.rst → llvm/docs/AMDGPU/gfx9_sdst_a319e6.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_sdst_6:
+.. _amdgpu_synid_gfx9_sdst_a319e6:
 
 sdst
 ====

diff --git a/llvm/docs/AMDGPU/gfx9_simm32_2.rst → llvm/docs/AMDGPU/gfx9_simm32_6f0844.rst b/llvm/docs/AMDGPU/gfx9_simm32_2.rst → llvm/docs/AMDGPU/gfx9_simm32_6f0844.rst
@@ -5,10 +5,10 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_simm32_2:
+.. _amdgpu_synid_gfx9_simm32_6f0844:
 
 simm32
 ======
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
-The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
+The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx9_simm32.rst → llvm/docs/AMDGPU/gfx9_simm32_a3e80c.rst b/llvm/docs/AMDGPU/gfx9_simm32.rst → llvm/docs/AMDGPU/gfx9_simm32_a3e80c.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_simm32:
+.. _amdgpu_synid_gfx9_simm32_a3e80c:
 
 simm32
 ======

diff --git a/llvm/docs/AMDGPU/gfx9_simm32_1.rst → llvm/docs/AMDGPU/gfx9_simm32_be0c1c.rst b/llvm/docs/AMDGPU/gfx9_simm32_1.rst → llvm/docs/AMDGPU/gfx9_simm32_be0c1c.rst
@@ -5,10 +5,10 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_simm32_1:
+.. _amdgpu_synid_gfx9_simm32_be0c1c:
 
 simm32
 ======
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
-The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
+The value is converted to *f16* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx9_soffset.rst → llvm/docs/AMDGPU/gfx9_soffset_4318ca.rst b/llvm/docs/AMDGPU/gfx9_soffset.rst → llvm/docs/AMDGPU/gfx9_soffset_4318ca.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_soffset:
+.. _amdgpu_synid_gfx9_soffset_4318ca:
 
 soffset
 =======

diff --git a/llvm/docs/AMDGPU/gfx9_soffset_1.rst → llvm/docs/AMDGPU/gfx9_soffset_8a17c8.rst b/llvm/docs/AMDGPU/gfx9_soffset_1.rst → llvm/docs/AMDGPU/gfx9_soffset_8a17c8.rst
@@ -5,16 +5,18 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_soffset_1:
+.. _amdgpu_synid_gfx9_soffset_8a17c8:
 
 soffset
 =======
 
-An offset added to the base address to get memory address.
+An offset from the base address.
 
 * If offset is specified as a register, it supplies an unsigned byte offset.
 * If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
 
+Note that an *immediate* offset may be specified using either :ref:`simm21<amdgpu_synid_simm21>` operand or :ref:`offset21s<amdgpu_synid_smem_offset21s>` modifier, but not both.
+
 *Size:* 1 dword.
 
 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx9_soffset_2.rst → llvm/docs/AMDGPU/gfx9_soffset_ba92ce.rst b/llvm/docs/AMDGPU/gfx9_soffset_2.rst → llvm/docs/AMDGPU/gfx9_soffset_ba92ce.rst
@@ -5,12 +5,14 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_soffset_2:
+.. _amdgpu_synid_gfx9_soffset_ba92ce:
 
 soffset
 =======
 
-An unsigned 20-bit offset added to the base address to get memory address.
+An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate.
+
+Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both.
 
 *Size:* 1 dword.
 

diff --git a/llvm/docs/AMDGPU/gfx9_src_3.rst → llvm/docs/AMDGPU/gfx9_src_089570.rst b/llvm/docs/AMDGPU/gfx9_src_3.rst → llvm/docs/AMDGPU/gfx9_src_089570.rst
@@ -5,7 +5,7 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid_gfx9_src_3:
+.. _amdgpu_synid_gfx9_src_089570:
 
 src
 ===