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GlobalISel: Fix incorrect lowering G_FCOPYSIGN
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In the basic case, this was reading the sign from the wrong operand.
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@arsenm
arsenm committed Apr 11, 2020
1 parent 6e7eeb4 commit 49ae0fc
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Showing 4 changed files with 281 additions and 195 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Expand Up @@ -4678,7 +4678,7 @@ LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
MachineInstr *Or;

if (Src0Ty == Src1Ty) {
auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
auto And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask);
Or = MIRBuilder.buildOr(Dst, And0, And1);
} else if (Src0Size > Src1Size) {
auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
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45 changes: 24 additions & 21 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
View file
Expand Up @@ -13,32 +13,35 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
Expand All @@ -63,7 +66,7 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_copysign_s32_s32
Expand All @@ -72,7 +75,7 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_copysign_s32_s32
Expand All @@ -81,7 +84,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
Expand All @@ -102,7 +105,7 @@ body: |
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
; SI: $vgpr0_vgpr1 = COPY [[OR]](s64)
; VI-LABEL: name: test_copysign_s64_s64
Expand All @@ -111,7 +114,7 @@ body: |
; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
; VI: $vgpr0_vgpr1 = COPY [[OR]](s64)
; GFX9-LABEL: name: test_copysign_s64_s64
Expand All @@ -120,7 +123,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
; GFX9: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
Expand Down Expand Up @@ -466,7 +469,7 @@ body: |
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; SI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST]]
; SI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
; SI: [[OR2:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; SI: $vgpr0 = COPY [[OR2]](<2 x s16>)
; VI-LABEL: name: test_copysign_v2s16_v2s16
Expand All @@ -482,7 +485,7 @@ body: |
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST1]]
; VI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BITCAST]]
; VI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
; VI: [[OR2:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; VI: $vgpr0 = COPY [[OR2]](<2 x s16>)
; GFX9-LABEL: name: test_copysign_v2s16_v2s16
Expand All @@ -493,7 +496,7 @@ body: |
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR_TRUNC1]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR_TRUNC]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BUILD_VECTOR_TRUNC]]
; GFX9: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; GFX9: $vgpr0 = COPY [[OR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
Expand All @@ -516,7 +519,7 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; SI: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; SI: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; SI: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
; SI: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
; SI: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
; VI-LABEL: name: test_copysign_v2s32_v2s32
Expand All @@ -527,7 +530,7 @@ body: |
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; VI: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; VI: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; VI: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
; VI: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
; VI: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
; GFX9-LABEL: name: test_copysign_v2s32_v2s32
Expand All @@ -538,7 +541,7 @@ body: |
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
; GFX9: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
; GFX9: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
Expand All @@ -561,7 +564,7 @@ body: |
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; SI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; SI: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; SI: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
Expand All @@ -576,7 +579,7 @@ body: |
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; VI: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; VI: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; VI: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
Expand All @@ -591,7 +594,7 @@ body: |
; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; GFX9: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
; GFX9: [[AND2:%[0-9]+]]:_(s64) = G_AND [[UV2]], [[C]]
; GFX9: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV3]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
Expand Down Expand Up @@ -767,7 +770,7 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_copysign_s32_s32_flagss
Expand All @@ -776,7 +779,7 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_copysign_s32_s32_flagss
Expand All @@ -785,7 +788,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
Expand Down
37 changes: 21 additions & 16 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
View file
Expand Up @@ -56,14 +56,16 @@ body: |
; SI-LABEL: name: test_frint_s64
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4841369599423283200
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4841369599423283200
; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[C1]], [[AND]]
; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[OR]]
; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
; SI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
; SI: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
; SI: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C1]]
; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FADD1]]
; SI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
; SI: $vgpr0_vgpr1 = COPY [[FRINT]](s64)
Expand Down Expand Up @@ -127,22 +129,25 @@ body: |
; SI-LABEL: name: test_frint_v2s64
; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4841369599423283200
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[COPY1]]
; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4841369599423283200
; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[C1]], [[AND]]
; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[OR]]
; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
; SI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
; SI: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x432FFFFFFFFFFFFF
; SI: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[UV]]
; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C1]]
; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FADD1]]
; SI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[UV]]
; SI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; SI: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[COPY2]]
; SI: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[COPY2]]
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C]]
; SI: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C1]], [[AND1]]
; SI: [[FADD2:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[OR1]]
; SI: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[OR1]]
; SI: [[FADD3:%[0-9]+]]:_(s64) = G_FADD [[FADD2]], [[FNEG1]]
; SI: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[UV1]]
; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS1]](s64), [[C1]]
; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS1]](s64), [[C2]]
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP1]](s1), [[UV1]], [[FADD3]]
; SI: [[FRINT1:%[0-9]+]]:_(s64) = G_FRINT [[UV1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FRINT]](s64), [[FRINT1]](s64)
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