SelectionDAG: allow FP extensions when folding extract/insert.

Before, we were trying to sign extend half -> float, and asserted in getNode.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -6149,6 +6149,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
         if (N1Op2C->getZExtValue() == N2C->getZExtValue()) {
           if (VT == N1.getOperand(1).getValueType())
             return N1.getOperand(1);
+          if (VT.isFloatingPoint()) {
+            assert(VT.getSizeInBits() > N1.getOperand(1).getValueType().getSizeInBits());
+            return getFPExtendOrRound(N1.getOperand(1), DL, VT);
+          }
           return getSExtOrTrunc(N1.getOperand(1), DL, VT);
         }
         return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);

llvm/test/CodeGen/ARM/arm-half-promote.ll

@@ -79,3 +79,16 @@ define fastcc { <8 x half>, <8 x half> } @f3() {
   ret { <8 x half>, <8 x half> } zeroinitializer
 }
 
+define void @extract_insert(ptr %dst) optnone noinline {
+; CHECK-LABEL: extract_insert:
+; CHECK: vmov.i32 d0, #0x0
+; CHECK: vcvtb.f16.f32 s0, s0
+; CHECK: vmov r1, s0
+; CHECK: strh r1, [r0]
+  %splat.splatinsert = insertelement <1 x half> zeroinitializer, half 0xH0000, i32 0
+  br label %next
+
+next:
+  store <1 x half> %splat.splatinsert, ptr %dst
+  ret void
+}